Hybrid and Heterogeneous Integration on Photonic Circuits: New Opportunities for Multifunctional Photonic Platforms

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Optics and Lasers".

Deadline for manuscript submissions: closed (10 July 2022) | Viewed by 27863

Special Issue Editor


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Guest Editor
Nokia Bell Labs France, III-V Lab, 1 Avenue Augustin Fresnel, 91767 Palaiseau, France
Interests: hybrid III-V/Si photonic integrated circuits for high-speed optical communication; sensing and optical computing
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Special Issue Information

Dear Colleagues,

The field of Silicon Photonics has rapidly evolved over the last few years, supported by the gain in maturity of the technology, design tools, and methods employed. The quest for new ideas and concepts to deploy low-cost, compact, and power-efficient photonic circuits with a high wafer yield and robustness that are able to meet the requirements in several application domains has triggered a frenetic activity worldwide. Presently, photonic circuit technology has diversified its number of available platforms. Despite the fact that indium phosphide (InP) and silicon-on-insulator (SOI) platforms are still considered as the warhorses of integrated photonics in terms of maturity and deployment of active (InP) and passive (SOI) components, other alternatives such as germanium-on-silicon, silicon nitride-on-insulator or hybrid solutions combining different functional materials and Si are gaining momentum. A representative example is the hybrid III-V/Si platform, which has been used to develop on-chip tunable lasers for wavelength division multiplexing purposes.

Indeed, the possibility to integrate several materials in a single photonic technology represents an attractive playground scenario to explore novel functionalities not available before in monolithic approaches. In this regard, the implementation of multifunctional photonic circuits that collect, transmit or reconfigure data in real-time conditions while interacting with their environment may open the route for a new class of photonic circuits with a wide range of possibilities and applications.  

This Special Issue will focus on recent advancements on hybrid and heterogeneous photonic circuits spanning from materials, processing techniques, and implementation of novel components, devices, and circuits employing diverse materials to enable multifunctional photonic platforms. With a combination of invited and contributed papers, this issue will survey the state-of-the-art of hybrid and heterogeneous photonic circuit technology.

Dr. Joan Manel Ramírez
Guest Editor

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Keywords

  • Silicon photonics
  • Photonic integrated circuits (PICs)
  • Heterogeneous integration
  • Multifunctional photonics
  • Reconfigurable photonics
  • Waveguides
  • Integrated lasers and semiconductor optical amplifiers (SOAs)
  • Indium phosphide photonics
  • Wafer bonding, die bonding
  • Optical communications
  • Sensors and actuators
  • High-speed optical components
  • 3D Photonics
  • Functional materials for photonics

Published Papers (7 papers)

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Research

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9 pages, 1836 KiB  
Communication
High-Q TeO2–Si Hybrid Microring Resonators
by Khadijeh Miarabbas Kiani, Dawson B. Bonneville, Andrew P. Knights and Jonathan D. B. Bradley
Appl. Sci. 2022, 12(3), 1363; https://0-doi-org.brum.beds.ac.uk/10.3390/app12031363 - 27 Jan 2022
Cited by 3 | Viewed by 1875
Abstract
We present the design and experimental measurement of tellurium oxide-clad silicon microring resonators with internal Q factors of up to 1.5 × 106, corresponding to a propagation loss of 0.42 dB/cm at wavelengths around 1550 nm. This compares to a propagation [...] Read more.
We present the design and experimental measurement of tellurium oxide-clad silicon microring resonators with internal Q factors of up to 1.5 × 106, corresponding to a propagation loss of 0.42 dB/cm at wavelengths around 1550 nm. This compares to a propagation loss of 3.4 dB/cm for unclad waveguides and 0.97 dB/cm for waveguides clad with SiO2. We compared our experimental results with the Payne–Lacey model describing propagation dominated by sidewall scattering. We conclude that the relative increase in the refractive index of TeO2 reduces scattering sufficiently to account for the low propagation loss. These results, in combination with the promising optical properties of TeO2, provide a further step towards realizing compact, monolithic, and low-loss passive, nonlinear, and rare-earth-doped active integrated photonic devices on a silicon photonic platform. Full article
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10 pages, 1772 KiB  
Article
Low-Threshold, High-Power On-Chip Tunable III-V/Si Lasers with Integrated Semiconductor Optical Amplifiers
by Joan Manel Ramírez, Pierre Fanneau de la Horie, Jean-Guy Provost, Stéphane Malhouitre, Delphine Néel, Christophe Jany, Claire Besancon, Nicolas Vaissière, Jean Decobert, Karim Hassan and David Bitauld
Appl. Sci. 2021, 11(23), 11096; https://0-doi-org.brum.beds.ac.uk/10.3390/app112311096 - 23 Nov 2021
Cited by 7 | Viewed by 2682
Abstract
Heterogeneously integrated III-V/Si lasers and semiconductor optical amplifiers (SOAs) are key devices for integrated photonics applications requiring miniaturized on-chip light sources, such as in optical communications, sensing, or spectroscopy. In this work, we present a widely tunable laser co-integrated with a semiconductor optical [...] Read more.
Heterogeneously integrated III-V/Si lasers and semiconductor optical amplifiers (SOAs) are key devices for integrated photonics applications requiring miniaturized on-chip light sources, such as in optical communications, sensing, or spectroscopy. In this work, we present a widely tunable laser co-integrated with a semiconductor optical amplifier in a heterogeneous platform that combines AlGaInAs multiple quantum wells (MQWs) and InP-based materials with silicon-on-insulator (SOI) wafers containing photonic integrated circuits. The co-integrated device is compact, has a total device footprint of 0.5 mm2, a lasing current threshold of 10 mA, a selectable wavelength tuning range of 50 nm centered at λ = 1549 nm, a fiber-coupled output power of 10 mW, and a laser linewidth of ν = 259 KHz. The SOA provides an on-chip gain of 18 dB/mm. The total power consumption of the co-integrated devices remains below 0.5 W even for the most power demanding lasing wavelengths. Apart from the above-mentioned applications, the co-integration of compact widely tunable III-V/Si lasers with on-chip SOAs provides a step forward towards the development of highly efficient, portable, and low power systems for wavelength division multiplexed passive optical networks (WDM-PONs). Full article
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10 pages, 2883 KiB  
Article
Oblique Deposition of Ti/Pt/Au Electrode on Photonic Crystal for Vertical Current Injection
by Hanqiao Ye, Ryota Saeki, Yifan Xiong, Takashi Kogure, Masato Morifuji, Hirotake Kajii, Akihiro Maruta and Masahiko Kondow
Appl. Sci. 2020, 10(23), 8377; https://0-doi-org.brum.beds.ac.uk/10.3390/app10238377 - 25 Nov 2020
Cited by 4 | Viewed by 1783
Abstract
We describe a device for inter-chip or intra-chip optical communications that contains the Circular Defect in photonic crystal (CirD) lasers array driven by vertical current injection. In order to improve the conductivity of the structure while also preventing current leakage, we introduce the [...] Read more.
We describe a device for inter-chip or intra-chip optical communications that contains the Circular Defect in photonic crystal (CirD) lasers array driven by vertical current injection. In order to improve the conductivity of the structure while also preventing current leakage, we introduce the oblique deposition of electrodes on a photonic crystal pattern by using an electron beam evaporation apparatus. The performance of an electrode is investigated by a transmission line method, and the CirD structure is fabricated with the electrode. We analyze the voltage-current relationship and confirm the CirD structure’s low resistance of under 1 kΩ. Full article
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Review

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17 pages, 6232 KiB  
Review
AlGaInAs Multi-Quantum Well Lasers on Silicon-on-Insulator Photonic Integrated Circuits Based on InP-Seed-Bonding and Epitaxial Regrowth
by Claire Besancon, Delphine Néel, Dalila Make, Joan Manel Ramírez, Giancarlo Cerulo, Nicolas Vaissiere, David Bitauld, Frédéric Pommereau, Frank Fournel, Cécilia Dupré, Hussein Mehdi, Franck Bassani and Jean Decobert
Appl. Sci. 2022, 12(1), 263; https://0-doi-org.brum.beds.ac.uk/10.3390/app12010263 - 28 Dec 2021
Cited by 6 | Viewed by 3262
Abstract
The tremendous demand for low-cost, low-consumption and high-capacity optical transmitters in data centers challenges the current InP-photonics platform. The use of silicon (Si) photonics platform to fabricate photonic integrated circuits (PICs) is a promising approach for low-cost large-scale fabrication considering the CMOS-technology maturity [...] Read more.
The tremendous demand for low-cost, low-consumption and high-capacity optical transmitters in data centers challenges the current InP-photonics platform. The use of silicon (Si) photonics platform to fabricate photonic integrated circuits (PICs) is a promising approach for low-cost large-scale fabrication considering the CMOS-technology maturity and scalability. However, Si itself cannot provide an efficient emitting light source due to its indirect bandgap. Therefore, the integration of III-V semiconductors on Si wafers allows us to benefit from the III-V emitting properties combined with benefits offered by the Si photonics platform. Direct epitaxy of InP-based materials on 300 mm Si wafers is the most promising approach to reduce the costs. However, the differences between InP and Si in terms of lattice mismatch, thermal coefficients and polarity inducing defects are challenging issues to overcome. III-V/Si hetero-integration platform by wafer-bonding is the most mature integration scheme. However, no additional epitaxial regrowth steps are implemented after the bonding step. Considering the much larger epitaxial toolkit available in the conventional monolithic InP platform, where several epitaxial steps are often implemented, this represents a significant limitation. In this paper, we review an advanced integration scheme of AlGaInAs-based laser sources on Si wafers by bonding a thin InP seed on which further regrowth steps are implemented. A 3 µm-thick AlGaInAs-based MutiQuantum Wells (MQW) laser structure was grown onto on InP-SiO2/Si (InPoSi) wafer and compared to the same structure grown on InP wafer as a reference. The 400 ppm thermal strain on the structure grown on InPoSi, induced by the difference of coefficient of thermal expansion between InP and Si, was assessed at growth temperature. We also showed that this structure demonstrates laser performance similar to the ones obtained for the same structure grown on InP. Therefore, no material degradation was observed in spite of the thermal strain. Then, we developed the Selective Area Growth (SAG) technique to grow multi-wavelength laser sources from a single growth step on InPoSi. A 155 nm-wide spectral range from 1515 nm to 1670 nm was achieved. Furthermore, an AlGaInAs MQW-based laser source was successfully grown on InP-SOI wafers and efficiently coupled to Si-photonic DBR cavities. Altogether, the regrowth on InP-SOI wafers holds great promises to combine the best from the III-V monolithic platform combined with the possibilities offered by the Si photonics circuitry via efficient light-coupling. Full article
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11 pages, 2182 KiB  
Review
In-Plane Monolithic Integration of Scaled III-V Photonic Devices
by Markus Scherrer, Noelia Vico Triviño, Svenja Mauthe, Preksha Tiwari, Heinz Schmid and Kirsten E. Moselund
Appl. Sci. 2021, 11(4), 1887; https://0-doi-org.brum.beds.ac.uk/10.3390/app11041887 - 21 Feb 2021
Cited by 9 | Viewed by 3026
Abstract
It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the [...] Read more.
It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits. Full article
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21 pages, 42290 KiB  
Review
Development of an Epitaxial Growth Technique Using III-V on a Si Platform for Heterogeneous Integration of Membrane Photonic Devices on Si
by Takuro Fujii, Tatsurou Hiraki, Takuma Aihara, Hidetaka Nishi, Koji Takeda, Tomonari Sato, Takaaki Kakitsuka, Tai Tsuchizawa and Shinji Matsuo
Appl. Sci. 2021, 11(4), 1801; https://0-doi-org.brum.beds.ac.uk/10.3390/app11041801 - 18 Feb 2021
Cited by 11 | Viewed by 6326
Abstract
The rapid increase in total transmission capacity within and between data centers requires the construction of low-cost, high-capacity optical transmitters. Since a tremendous number of transmitters are required, photonic integrated circuits (PICs) using Si photonics technology enabling the integration of various functional devices [...] Read more.
The rapid increase in total transmission capacity within and between data centers requires the construction of low-cost, high-capacity optical transmitters. Since a tremendous number of transmitters are required, photonic integrated circuits (PICs) using Si photonics technology enabling the integration of various functional devices on a single chip is a promising solution. A limitation of a Si-based PIC is the lack of an efficient light source due to the indirect bandgap of Si; therefore, hybrid integration technology of III-V semiconductor lasers on Si is desirable. The major challenges are that heterogeneous integration of III-V materials on Si induces the formation of dislocation at high process temperature; thus, the epitaxial regrowth process is difficult to apply. This paper reviews the evaluations conducted on our epitaxial growth technique using a directly bonded III-V membrane layer on a Si substrate. This technique enables epitaxial growth without the fundamental difficulties associated with lattice mismatch or anti-phase boundaries. In addition, crystal degradation correlating with the difference in thermal expansion is eliminated by keeping the total III-V layer thickness thinner than ~350 nm. As a result, various III-V photonic-device-fabrication technologies, such as buried regrowth, butt-joint regrowth, and selective area growth, can be applicable on the Si-photonics platform. We demonstrated the growth of indium-gallium-aluminum arsenide (InGaAlAs) multi-quantum wells (MQWs) and fabrication of lasers that exhibit >25 Gbit/s direct modulation with low energy cost. In addition, selective-area growth that enables the full O-band bandgap control of the MQW layer over the 150-nm range was demonstrated. We also fabricated indium-gallium-arsenide phosphide (InGaAsP) based phase modulators integrated with a distributed feedback laser. Therefore, the directly bonded III-V-on-Si substrate platform paves the way to manufacturing hybrid PICs for future data-center networks. Full article
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34 pages, 8274 KiB  
Review
CORNERSTONE’s Silicon Photonics Rapid Prototyping Platforms: Current Status and Future Outlook
by Callum G. Littlejohns, David J. Rowe, Han Du, Ke Li, Weiwei Zhang, Wei Cao, Thalia Dominguez Bucio, Xingzhao Yan, Mehdi Banakar, Dehn Tran, Shenghao Liu, Fanfan Meng, Bigeng Chen, Yanli Qi, Xia Chen, Milos Nedeljkovic, Lorenzo Mastronardi, Rijan Maharjan, Sanket Bohora, Ashim Dhakal, Iain Crowe, Ankur Khurana, Krishna C. Balram, Luca Zagaglia, Francesco Floris, Peter O’Brien, Eugenio Di Gaetano, Harold M.H. Chong, Frederic Y. Gardes, David J. Thomson, Goran Z. Mashanovich, Marc Sorel and Graham T. Reedadd Show full author list remove Hide full author list
Appl. Sci. 2020, 10(22), 8201; https://0-doi-org.brum.beds.ac.uk/10.3390/app10228201 - 19 Nov 2020
Cited by 26 | Viewed by 7812
Abstract
The field of silicon photonics has experienced widespread adoption in the datacoms industry over the past decade, with a plethora of other applications emerging more recently such as light detection and ranging (LIDAR), sensing, quantum photonics, programmable photonics and artificial intelligence. As a [...] Read more.
The field of silicon photonics has experienced widespread adoption in the datacoms industry over the past decade, with a plethora of other applications emerging more recently such as light detection and ranging (LIDAR), sensing, quantum photonics, programmable photonics and artificial intelligence. As a result of this, many commercial complementary metal oxide semiconductor (CMOS) foundries have developed open access silicon photonics process lines, enabling the mass production of silicon photonics systems. On the other side of the spectrum, several research labs, typically within universities, have opened up their facilities for small scale prototyping, commonly exploiting e-beam lithography for wafer patterning. Within this ecosystem, there remains a challenge for early stage researchers to progress their novel and innovate designs from the research lab to the commercial foundries because of the lack of compatibility of the processing technologies (e-beam lithography is not an industry tool). The CORNERSTONE rapid-prototyping capability bridges this gap between research and industry by providing a rapid prototyping fabrication line based on deep-UV lithography to enable seamless scaling up of production volumes, whilst also retaining the ability for device level innovation, crucial for researchers, by offering flexibility in its process flows. This review article presents a summary of the current CORNERSTONE capabilities and an outlook for the future. Full article
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