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Applied Sciences
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Programmable Logic Controllers
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Programmable Logic Controllers

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: closed (30 December 2021) | Viewed by 17155

Special Issue Editors

Prof. Dr. Dariusz Kania

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Guest Editor
Department of Digital Systems, Silesian University of Technology, Akademicka 16, 44-100 Gliwice, Poland
Interests: programmable devices and systems; logic synthesis; technology mapping; optimization of digital circuits; low-power devices; binary decision diagram; high-level synthesis; finite state machines; programmable logic controller; microprocessor systems; embedded systems; music data mining; computer posturography in the postural control diagnostics and motor functions rehabilitation
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Robert Czerwiński

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Guest Editor
Department of Digital Systems, Silesian University of Technology, Gliwice, Poland
Interests: programmable logic devices, design of digital circuits in Verilog HDL, logic synthesis with particular emphasis on the sequential automata, decomposition, technological mapping, programmable logic controllers, RISC-V microprocessors
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Programmable logic controllers (PLCs) form an important technological basis for manufacturing automation. In the era of the fourth Industrial revolution (Industry 4.0), PLCs must fulfill a range of requirements, resulting from new production conditions. However, programmable logic controllers will continue to be required to a considerable extent for the production of tomorrow in order to cut production costs, increase quality, etc. Programmable technology with multiprocessor systems-on-a-chip (MPSoC) brings new possibilities for constructing new PLCs, central processing units, function blocks, application-specific blocks, and others.

The purpose of this Special Issue is to provide a possibility for scientists and practitioners related to programmable logic controller to present their research. Topics of interest focus on (but are not limited to) the hardware aspects in which innovations bring significant improvements in the system performance:

  • PLC / CPU / function blocks design;
  • Fuzzy logic controllers;
  • Reconfigurable controllers;
  • Intelligent control and systems;
  • Hardware implementation of control programs;
  • Competitor and distributed control systems;
  • Industrial networks;
  • Control systems, concurrent control systems, automatic control and robotics;
  • Distributed and networked control systems;
  • Control algorithms and methodologies;
  • Design methodologies of PLC;
  • Model-based design, including model-driven development, unified modeling language (UML, SysML), etc .;
  • Concurrency modeling and analysis, including Petri net-based control systems;
  • Optimization techniques of PLC;
  • Verification and validation techniques, including formal verification methods;
  • Integrated tool suits for PLC design, analysis and verification;
  • Computation models, including mathematical descriptions and models;
  • Real-time systems, including real-time sensing and computing;
  • Embedded systems;
  • Networked embedded systems;
  • Internet of things, including aspects of designing, organization and implementation of control systems;
  • Cyberphysical systems and Industry 4.0.

Pro. Dr. Dariusz Kania
Pro. Dr. Robert Czerwiński
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Programmable logic controller
  • PLC
  • PLC central processing unit
  • function blocks
  • IEC 61131
  • control system
  • automation system
  • control program
  • automatic control
  • ladder logic
  • sequential function charts

Published Papers (6 papers)

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Research

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17 pages, 59474 KiB  
Article
Application of the MiL and HiL Simulation Techniques in Stewart Platform Control Development
by Dominik Walica and Petr Noskievič
Appl. Sci. 2022, 12(5), 2323; https://0-doi-org.brum.beds.ac.uk/10.3390/app12052323 - 23 Feb 2022
Cited by 2 | Viewed by 2832
Abstract
During the integration phase of a system development, we are often concerned as to whether the designed control algorithm could be performed on the selected controller in real-time. One of the tools to test and validate the control scheme is the Hardware-in-the-Loop (HiL) [...] Read more.
During the integration phase of a system development, we are often concerned as to whether the designed control algorithm could be performed on the selected controller in real-time. One of the tools to test and validate the control scheme is the Hardware-in-the-Loop (HiL) simulation technique, which is a part of a model-based design methodology. This approach requires a simulation model of a controlled system running in a real-time loop with an intended controller and a control algorithm, which are objects of interest in this method. To perform the test, the control algorithm must be deployed to the controller such as a PLC. This paper presents a use case of the HiL technique in the design of the Stewart platform control, where the controller is PLCnext from Phoenix Contact. The control algorithm was first verified in the Model-in-the-Loop simulation (MiL) and then generated as a code from the Matlab/Simulink environment and deployed to the PLCnext, which resulted in a smoother transition from the design to the integration and testing phase. The presented method is also applicable to other controllers that support code generation. Full article
(This article belongs to the Special Issue Programmable Logic Controllers)
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23 pages, 4531 KiB  
Article
FPGA Implementation of IEC-61131-3-Based Hardware Aided Counters for PLC
by Miroslaw Chmiel, Robert Czerwinski and Andrzej Malcher
Appl. Sci. 2021, 11(21), 10183; https://0-doi-org.brum.beds.ac.uk/10.3390/app112110183 - 30 Oct 2021
Cited by 3 | Viewed by 1852
Abstract
The article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are designed as the FPGA built-in memory blocks with a single [...] Read more.
The article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are designed as the FPGA built-in memory blocks with a single common executing unit. These solutions are compared to each other and compared with counters realized in commercially available PLCs like Siemens SIMATIC S7 controllers. The structure of integrated hardware–software CPU with counters is presented. The paper presents how the designer can take advantage of the specific features of the FPGA devices to optimize both the utilization of resources and speed of realization of the particular blocks. Experimental results prove the high efficiency of the proposed solutions. Full article
(This article belongs to the Special Issue Programmable Logic Controllers)
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15 pages, 16521 KiB  
Article
Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions
by Zulfikar Zulfikar, Norhayati Soin, Sharifah Fatmadiana Wan Muhamad Hatta, Mohamad Sofian Abu Talip and Anuar Jaafar
Appl. Sci. 2021, 11(20), 9730; https://0-doi-org.brum.beds.ac.uk/10.3390/app11209730 - 18 Oct 2021
Cited by 4 | Viewed by 1594
Abstract
The research into ring oscillator physically unclonable functions (RO-PUF) continues to expand due to its simple structure, ease of generating responses, and its promises of primitive security. However, a substantial study has yet to be carried out in developing designs of the FPGA-based [...] Read more.
The research into ring oscillator physically unclonable functions (RO-PUF) continues to expand due to its simple structure, ease of generating responses, and its promises of primitive security. However, a substantial study has yet to be carried out in developing designs of the FPGA-based RO-PUF, which effectively balances performance and area efficiency. This work proposes a modified RO-PUF where the ring oscillators are connected directly to the counters. The proposed RO-PUF requires fewer RO than the conventional structure since this work utilizes the direct pulse count method. This work aims to seek the ideal routing density of ROs to improve uniqueness. For this purpose, five logic arrangements of a wide range of routing densities of ROs were tested. Upon implementation onto the FPGA chip, the routing density of ROs are varied significantly in terms of wire utilization (higher than 25%) and routing hotspots (higher than 80%). The best uniqueness attained was 52.71%, while the highest reliability was 99.51%. This study improves the uniqueness by 2% subsequent to the application of scenarios to consider ROs with a narrow range of routing density. The best range of wire utilization and routing hotspots of individual RO in this work is 3–5% and 20–50%, respectively. The performance metrics (uniqueness and reliability) of the proposed RO-PUF are much better than existing works using a similar FPGA platform (Altera), and it is as good as the recent RO-PUFs realized on Xilinx. Additionally, this work estimates the minimum runtimes to reduce error and response bit-flip of RO-PUF. Full article
(This article belongs to the Special Issue Programmable Logic Controllers)
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21 pages, 2170 KiB  
Article
Reconfigurable Logic Controller—Direct FPGA Synthesis Approach
by Adam Milik, Marcin Kubica and Dariusz Kania
Appl. Sci. 2021, 11(18), 8515; https://0-doi-org.brum.beds.ac.uk/10.3390/app11188515 - 14 Sep 2021
Cited by 6 | Viewed by 2523
Abstract
Programmable logic controllers are commonly used in automation systems. Continuously growing demands result in the growth of control program complexity. The classic approach, based on programmatic serial-cyclic execution, results in an unacceptable extension of response time. To overcome long response time massive parallel [...] Read more.
Programmable logic controllers are commonly used in automation systems. Continuously growing demands result in the growth of control program complexity. The classic approach, based on programmatic serial-cyclic execution, results in an unacceptable extension of response time. To overcome long response time massive parallel program execution is proposed. It utilize direct in hardware program implementation in field programmable devices. The paper brings a formal method of representing control programs using flow graphs and enabling single cycle computations. The developed method accepts ladder diagrams (LD) and sequential function charts (SFC), according to IEC61131-3 standard requirements. It is capable of handling logic and arithmetic computations, enabling its hardware mapping. The intermediate form is optimized using flow graph representation and BDDs for analyzing logic dependencies. The BDD representation of logic dependencies enables direct mapping to lookup tables of a selected FPGA family. All the above steps deliver high-performance and direct hardware implementation of the control program given by standard languages. The controller response time is short, predictable, and independent from logic conditions during program execution. Full article
(This article belongs to the Special Issue Programmable Logic Controllers)
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19 pages, 27475 KiB  
Article
Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance
by Anuar Jaafar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim and Zahriladha Zakaria
Appl. Sci. 2021, 11(14), 6417; https://0-doi-org.brum.beds.ac.uk/10.3390/app11146417 - 12 Jul 2021
Viewed by 2036
Abstract
The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining [...] Read more.
The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances. Full article
(This article belongs to the Special Issue Programmable Logic Controllers)
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Review

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26 pages, 1271 KiB  
Review
Security Challenges in Industry 4.0 PLC Systems
by Janusz Hajda, Ryszard Jakuszewski and Szymon Ogonowski
Appl. Sci. 2021, 11(21), 9785; https://0-doi-org.brum.beds.ac.uk/10.3390/app11219785 - 20 Oct 2021
Cited by 26 | Viewed by 4735
Abstract
The concept of the fourth industrial revolution assumes the integration of people and digitally controlled machines with the Internet and information technologies. At the end of 2015, more than 20 billion machines and devices were connected to the Internet, with an expected growth [...] Read more.
The concept of the fourth industrial revolution assumes the integration of people and digitally controlled machines with the Internet and information technologies. At the end of 2015, more than 20 billion machines and devices were connected to the Internet, with an expected growth to half a trillion by 2030. The most important raw material for this digital revolution is data, which when properly stored, analyzed and secured, constitute the basis for the development of any business. In times of rapid industrial development, automation of production processes and systems integration via networks, the effective protection of the cyber-physical systems of a plant is particularly important. To minimize the risks associated with Internet access, one must define all the possible threats and determine their sources in the plant and block or minimize the possibility of sabotage or data loss. This article analyzes the security measures used in industrial systems. In particular, risk management and the study of the risk sources in terms of human, hardware and software aspects in networked PLC and SCADA systems are discussed. Methods of improving the architecture of industrial networks and their management are proposed in order to increase the level of security. Additionally, the safety of the communication protocols with PLCs in industrial control systems is discussed. Full article
(This article belongs to the Special Issue Programmable Logic Controllers)
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