Design and Simulation of Electrostatic Protection Device on Semiconductors
A special issue of Materials (ISSN 1996-1944). This special issue belongs to the section "Electronic Materials".
Deadline for manuscript submissions: closed (10 August 2023) | Viewed by 2507
Special Issue Editors
Interests: ESD protection device design; simulation and modeling; system-level ESD protection
Interests: ESD protection designs; biomimetic circuit designs
Interests: ESD protection; latchup prevention; semiconductor devices
Interests: CMOS integrated circuits; high-k dielectric thin films; nanoelectronics; semiconductor device models; MOSFET; approximation theory; ballistic transport; circuit optimisation; electrostatics; elemental semiconductors; field effect transistors; nanowires; numerical analysis; sensitivity; silicon; surface potential; surface roughness; silicon compounds; dielectric thin films; tunnelling; interface states; X-ray photoelectron spectra; electron traps; hafnium compounds; SPICE
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Special Issue Information
Dear Colleagues,
Electrostatic discharge (ESD) is one of the most prevalent threats to the reliability of electronic components. ESD involves the transfer of a finite amount of charge from one object (e.g., a human body) to another (e.g., a microchip), and accounts for more than 35% of all catastrophic chip damage due to single events, as it can result in a very high current passing through the microchip in a very short period of time. In order to protect integrated circuits from ESD stress, semiconductor manufacturers place a high priority on the design of on-chip ESD structures. With advancements in MOS processing technology, ESD-induced failures are becoming more common. Furthermore, it is becoming increasingly difficult for semiconductor companies worldwide to meet the progressively more stringent ESD protection requirements for various electronic applications, and we can anticipate that the availability of effective and robust ESD protection solutions will become essential to the commercialization of future and modern electronics. Latchup also poses a reliability threat, as it may occur during normal chip operation and lead to a runaway event that causes the chip to be destroyed. Therefore, Latchup mitigation solutions are also urgently needed in the semiconductor industry.
The main objective of this dedicated Special Issue is to engage the global ESD and Latchup community in a serious discussion through scholarly contributions specifically focused on solving major challenges in the board area of ESD and Latchup solutions for semiconductor technologies.
Dr. Zhiwei Liu
Prof. Dr. Chun-Yu Lin
Dr. Wei Liang
Prof. Dr. Hei Wong
Guest Editors
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Keywords
- ESD protection devices
- latchup immunity
- low capacitance
- holding voltage
- turn-on speed
- CDM protection
- power clamp
- TCAD simulation
- ESD devices modeling
