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Nanomaterials
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Abridging the CMOS Technology
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Abridging the CMOS Technology

A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: closed (31 August 2022) | Viewed by 28110

Special Issue Editor

Prof. Dr. Hei Wong

E-Mail Website
Guest Editor
Department of Electrical Engineering, City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong, China
Interests: CMOS integrated circuits; high-k dielectric thin films; nanoelectronics; semiconductor device models; MOSFET; approximation theory; ballistic transport; circuit optimisation; electrostatics; elemental semiconductors; field effect transistors; nanowires; numerical analysis; sensitivity; silicon; surface potential; surface roughness; silicon compounds; dielectric thin films; tunnelling; interface states; X-ray photoelectron spectra; electron traps; hafnium compounds, SPICE
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

From either a physics device, fabrication technology, or process economics point of view, the downsizing of silicon-based CMOS devices will shortly be over. Although new revolutionized materials and new technologies for further integrated electronics advancement are on the horizon already, considering the development of nanoscale-sized devices, as well as giga-scale in integration density, complexity in fabrication technology, and the widespread application of the present CMOS technology, which is a cumulative outcome resulted from the relentless advancement and innovation of over seven decades, the emerging new materials and new devices are unlikely to replace CMOS technology in the short term. A possible scenario is that the existing CMOS technology will still be, at baseline, the mainstream integration technology for decades to come; alongside this, new material discovery and new technology innovation, on the one hand, could serve as technological options for overcoming some of the constraints in CMOS devices and fabrication technology, and, on the other hand, could enrich and enhance the CMOS technology in certain aspects.    

This Special Issue, titled “Abridging the CMOS Technology”, serves as a forum for multi-disciplinary experts to address various aspects of recent advancements in nanomaterials and nanotechnology that could be abridged to further CMOS technology advancement at the end of More Moore. The format of articles includes full papers, communications, and reviews. Topics include but are not limited to:

  • CMOS device characteristic enhancement with nanomaterials;
  • Nanotechnology for CMOS fabrication;
  • Silicon and 2D material integration;
  • Silicon/2D material interaction and characterization;
  • Enriching CMOS technology with 2D material-based devices, sensors and transducers;
  • Nanophotonics–CMOS integration;
  • Interconnects with nanomaterials;
  • Nanoscale modeling and computation;
  • CMOS thermal management with nanomaterials.

Prof. Dr. Hei Wong
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Nanomaterials is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2900 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • CMOS device
  • 2D material-based devices
  • sensors
  • transducers
  • nanophotonics

Published Papers (10 papers)

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Editorial

Jump to: Research, Review

3 pages, 159 KiB  
Editorial
Abridging CMOS Technology
by Hei Wong
Nanomaterials 2022, 12(23), 4245; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12234245 - 29 Nov 2022
Cited by 4 | Viewed by 1160
Abstract
Whether from a device physics, fabrication technology, or process economics point of view, the practice of downsizing silicon-based CMOS devices will soon end [...] Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)

Research

Jump to: Editorial, Review

16 pages, 3238 KiB  
Article
Device Modeling of Organic Photovoltaic Cells with Traditional and Inverted Cells Using s-SWCNT:C60 as Active Layer
by Vijai M. Moorthy and Viranjay M. Srivastava
Nanomaterials 2022, 12(16), 2844; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12162844 - 18 Aug 2022
Cited by 9 | Viewed by 1650
Abstract
This research work presents a thorough analysis of Traditional Organic Solar Cell (TOSC) and novel designed Inverted OSC (IOSC) using Bulk Hetero-Junction (BHJ) structure. Herein, 2D photovoltaic device models were used to observe the results of the semiconducting Single Wall Carbon Nanotube (s-SWCNT):C [...] Read more.
This research work presents a thorough analysis of Traditional Organic Solar Cell (TOSC) and novel designed Inverted OSC (IOSC) using Bulk Hetero-Junction (BHJ) structure. Herein, 2D photovoltaic device models were used to observe the results of the semiconducting Single Wall Carbon Nanotube (s-SWCNT):C60-based organic photovoltaic. This work has improved the BHJ photodiodes by varying the active layer thickness. The analysis has been performed at various active layer thicknesses from 50 to 300 nm using the active material s-SWCNT:C60. An analysis with various parameters to determine the most effective parameters for organic photovoltaic performance has been conducted. As a result, it has been established that IOSC has the maximum efficiency of 10.4%, which is higher than the efficiency of TOSC (9.5%). In addition, the active layer with the highest efficacy has been recorded using this material for both TOSC and IOSC Nano Photodiodes (NPDs). Furthermore, the diode structure and geometrical parameters have been optimized and compared to maximize the performance of photodiodes. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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5 pages, 1431 KiB  
Article
Silicon-Controlled Rectifier Embedded Diode for 7 nm FinFET Process Electrostatic Discharge Protection
by Xinyu Zhu, Shurong Dong, Fangjun Yu, Feifan Deng, Kalya Shubhakar, Kin Leong Pey and Jikui Luo
Nanomaterials 2022, 12(10), 1743; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12101743 - 19 May 2022
Cited by 5 | Viewed by 1737
Abstract
A new silicon-controlled rectifier embedded diode (SCR-D) for 7 nm bulk FinFET process electrostatic discharge (ESD) protection applications is proposed. The transmission line pulse (TLP) results show that the proposed device has a low turn-on voltage of 1.77 V. Compared with conventional SCR [...] Read more.
A new silicon-controlled rectifier embedded diode (SCR-D) for 7 nm bulk FinFET process electrostatic discharge (ESD) protection applications is proposed. The transmission line pulse (TLP) results show that the proposed device has a low turn-on voltage of 1.77 V. Compared with conventional SCR and diode string, the proposed SCR-D has an additional conduction path constituting by two additional inherent diodes, which results in a 1.8-to-2.2-times current surge capability as compared with the simple diode string and conventional SCR with the same size. The results show that the proposed device meets the 7 nm FinFET process ESD design window and has already been applied in actual circuits. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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15 pages, 3159 KiB  
Article
On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node
by Hei Wong and Kuniyuki Kakushima
Nanomaterials 2022, 12(10), 1739; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12101739 - 19 May 2022
Cited by 9 | Viewed by 6900
Abstract
This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by [...] Read more.
This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by the same lithography and dry etching capabilities of a foundry. The results show that the nanosheet structure has advantages only when the intersheet spacing or vertical sheet pitch is less than the sheet width. Additionally, for the nanowire transistors, the wire spacing should be less than 57% of the wire diameter in order to have a folding ratio better than a FinFET with the same total height and footprint. Considering the technological constraints for the gate oxide and metal gate thicknesses, the minimum intersheet/interwire spacing should be in the range of 7 to 8 nm. Then, the VNSFET structure has the advantage of boosting the chip density over the FinFET ones only when the sheet width is wider than 8 nm. On the other hand, the VNWFET structure may have a better footprint sizing than the FinFET ones only when the nanowire diameter is larger than 14 nm. In addition, considering the different channel mobilities along the different surface directions of the silicon channel and also some other unfavorable natures such as more complicated processes, more significant surface roughness scattering, and parasitic capacitance effects, the nanosheet transistor does not show superior scaling capability than the FinFET counterpart when approaching the ultimate technology node. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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11 pages, 10920 KiB  
Article
Robust Simulations of Nanoscale Phase Change Memory: Dynamics and Retention
by Feilong Ding, Deqi Dong, Yihan Chen, Xinnan Lin and Lining Zhang
Nanomaterials 2021, 11(11), 2945; https://0-doi-org.brum.beds.ac.uk/10.3390/nano11112945 - 03 Nov 2021
Cited by 3 | Viewed by 1962
Abstract
A robust simulation framework was developed for nanoscale phase change memory (PCM) cells. Starting from the reaction rate theory, the dynamic nucleation was simulated to capture the evolution of the cluster population. To accommodate the non-uniform critical sizes of nuclei due to the [...] Read more.
A robust simulation framework was developed for nanoscale phase change memory (PCM) cells. Starting from the reaction rate theory, the dynamic nucleation was simulated to capture the evolution of the cluster population. To accommodate the non-uniform critical sizes of nuclei due to the non-isothermal conditions during PCM cell programming, an improved crystallization model was proposed that goes beyond the classical nucleation and growth model. With the above, the incubation period in which the cluster distributions reached their equilibrium was captured beyond the capability of simulations with a steady-state nucleation rate. The implications of the developed simulation method are discussed regarding PCM fast SET programming and retention. This work provides the possibility for further improvement of PCM and integration with CMOS technology. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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14 pages, 48529 KiB  
Article
Numerical Investigation of Phononic Crystal Based Film Bulk Acoustic Wave Resonators
by Linhao Shi, Weipeng Xuan, Biao Zhang, Shurong Dong, Hao Jin and Jikui Luo
Nanomaterials 2021, 11(10), 2547; https://0-doi-org.brum.beds.ac.uk/10.3390/nano11102547 - 28 Sep 2021
Cited by 2 | Viewed by 2551
Abstract
Film bulk acoustic resonator (FBAR)-based filters have attracted great attention because they can be used to build high-performance RF filters with low cost and small device size. Generally, FBARs employ the air cavity and Bragg mirror to confine the acoustic energy within the [...] Read more.
Film bulk acoustic resonator (FBAR)-based filters have attracted great attention because they can be used to build high-performance RF filters with low cost and small device size. Generally, FBARs employ the air cavity and Bragg mirror to confine the acoustic energy within the piezoelectric layer, so as to achieve high quality factors and low insertion loss. Here, two-dimensional (2D) phononic crystals (PhCs) are proposed to be the acoustic energy reflection layer for an FBAR (PhC-FBAR). Four kinds of PhC structures are investigated, and their bandgap diagrams and acoustic wave reflection coefficients are analyzed using the finite element method (FEM). Then, the PhCs are used as the acoustic wave reflectors at the bottom of the piezoelectric stack, with high reflectivity for elastic waves in the specific frequency range. The results show that the specific PhC possesses a wide bandgap, which enables the PhC-FBAR to work at a broad frequency range. Furthermore, the impedance spectra of PhC-FBARs are very smooth with few spurious modes, and the quality factors are close to those of traditional FBARs with air cavities, showing the application potential of the PhC-FBAR filters with wide bandwidth and high power capability. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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10 pages, 2215 KiB  
Article
Characteristic Variabilities of Subnanometer EOT La2O3 Gate Dielectric Film of Nano CMOS Devices
by Hei Wong, Jieqiong Zhang, Hiroshi Iwai and Kuniyuki Kakushima
Nanomaterials 2021, 11(8), 2118; https://0-doi-org.brum.beds.ac.uk/10.3390/nano11082118 - 20 Aug 2021
Cited by 5 | Viewed by 2318
Abstract
As CMOS devices are scaled down to a nanoscale range, characteristic variability has become a critical issue for yield and performance control of gigascale integrated circuit manufacturing. Nanoscale in size, few monolayers thick, and less thermally stable high-k interfaces all together cause more [...] Read more.
As CMOS devices are scaled down to a nanoscale range, characteristic variability has become a critical issue for yield and performance control of gigascale integrated circuit manufacturing. Nanoscale in size, few monolayers thick, and less thermally stable high-k interfaces all together cause more significant surface roughness-induced local electric field fluctuation and thus leads to a large device characteristic variability. This paper presents a comprehensive study and detailed discussion on the gate leakage variabilities of nanoscale devices corresponding to the surface roughness effects. By taking the W/La2O3/Si structure as an example, capacitance and leakage current variabilities were found to increase pronouncedly for samples even with a very low-temperature thermal annealing at 300 °C. These results can be explained consistently with the increase in surface roughness as a result of local oxidation at the La2O3/Si interface and the interface reactions at the W/La2O3 interface. The surface roughness effects are expected to be severe in future generations’ devices with even thinner gate dielectric film and smaller size of the devices. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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Review

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60 pages, 21158 KiB  
Review
Application of Two-Dimensional Materials towards CMOS-Integrated Gas Sensors
by Lado Filipovic and Siegfried Selberherr
Nanomaterials 2022, 12(20), 3651; https://doi.org/10.3390/nano12203651 - 18 Oct 2022
Cited by 14 | Viewed by 3609
Abstract
During the last few decades, the microelectronics industry has actively been investigating the potential for the functional integration of semiconductor-based devices beyond digital logic and memory, which includes RF and analog circuits, biochips, and sensors, on the same chip. In the case of [...] Read more.
During the last few decades, the microelectronics industry has actively been investigating the potential for the functional integration of semiconductor-based devices beyond digital logic and memory, which includes RF and analog circuits, biochips, and sensors, on the same chip. In the case of gas sensor integration, it is necessary that future devices can be manufactured using a fabrication technology which is also compatible with the processes applied to digital logic transistors. This will likely involve adopting the mature complementary metal oxide semiconductor (CMOS) fabrication technique or a technique which is compatible with CMOS due to the inherent low costs, scalability, and potential for mass production that this technology provides. While chemiresistive semiconductor metal oxide (SMO) gas sensors have been the principal semiconductor-based gas sensor technology investigated in the past, resulting in their eventual commercialization, they need high-temperature operation to provide sufficient energies for the surface chemical reactions essential for the molecular detection of gases in the ambient. Therefore, the integration of a microheater in a MEMS structure is a requirement, which can be quite complex. This is, therefore, undesirable and room temperature, or at least near-room temperature, solutions are readily being investigated and sought after. Room-temperature SMO operation has been achieved using UV illumination, but this further complicates CMOS integration. Recent studies suggest that two-dimensional (2D) materials may offer a solution to this problem since they have a high likelihood for integration with sophisticated CMOS fabrication while also providing a high sensitivity towards a plethora of gases of interest, even at room temperature. This review discusses many types of promising 2D materials which show high potential for integration as channel materials for digital logic field effect transistors (FETs) as well as chemiresistive and FET-based sensing films, due to the presence of a sufficiently wide band gap. This excludes graphene from this review, while recent achievements in gas sensing with graphene oxide, reduced graphene oxide, transition metal dichalcogenides (TMDs), phosphorene, and MXenes are examined. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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19 pages, 6455 KiB  
Review
Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials
by Theresia Knobloch, Siegfried Selberherr and Tibor Grasser
Nanomaterials 2022, 12(20), 3548; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12203548 - 11 Oct 2022
Cited by 14 | Viewed by 3241
Abstract
For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional (2D) materials are a potential replacement for silicon since even atomically thin 2D semiconductors can maintain sizable mobilities and provide enhanced gate control in a stacked channel nanosheet transistor geometry. While theoretical [...] Read more.
For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional (2D) materials are a potential replacement for silicon since even atomically thin 2D semiconductors can maintain sizable mobilities and provide enhanced gate control in a stacked channel nanosheet transistor geometry. While theoretical projections and available experimental prototypes indicate great potential for 2D field effect transistors (FETs), several major challenges must be solved to realize CMOS logic circuits based on 2D materials at the wafer scale. This review discusses the most critical issues and benchmarks against the targets outlined for the 0.7 nm node in the International Roadmap for Devices and Systems scheduled for 2034. These issues are grouped into four areas; device scaling, the formation of low-resistive contacts to 2D semiconductors, gate stack design, and wafer-scale process integration. Here, we summarize recent developments in these areas and identify the most important future research questions which will have to be solved to allow for industrial adaptation of the 2D technology. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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21 pages, 13232 KiB  
Review
Selective Overview of 3D Heterogeneity in CMOS
by Cheng Li, Zijin Pan, Xunyu Li, Weiquan Hao, Runyu Miao and Albert Wang
Nanomaterials 2022, 12(14), 2340; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12142340 - 08 Jul 2022
Cited by 4 | Viewed by 1705
Abstract
As the demands for improved performance of integrated circuit (IC) chips continue to increase, while technology scaling driven by Moore’s law is becoming extremely challenging, if not impractical or impossible, heterogeneous integration (HI) emerges as an attractive pathway to further enhance performance of [...] Read more.
As the demands for improved performance of integrated circuit (IC) chips continue to increase, while technology scaling driven by Moore’s law is becoming extremely challenging, if not impractical or impossible, heterogeneous integration (HI) emerges as an attractive pathway to further enhance performance of Si-based complementary metal-oxide-semiconductor (CMOS) chips. The underlying basis for using HI technologies and structures is that IC performance goes well beyond classic logic functions; rather, functionalities and complexity of smart chips span across the full information chain, including signal sensing, conditioning, processing, storage, computing, communication, control, and actuation, which are required to facilitate comprehensive human–world interactions. Therefore, HI technologies can bring in more function diversifications to make system chips smarter within acceptable design constraints, including costs. Over the past two decades or so, a large number of HI technologies have been explored to increase heterogeneities in materials, technologies, devices, circuits, and system architectures, making it practically impossible to provide one single comprehensive review of everything in the field in one paper. This article chooses to offer a topical overview of selected HI structures that have been validated in CMOS platforms, including a stacked-via vertical magnetic-cored inductor structure in CMOSs, a metal wall structure in the back end of line (BEOL) of CMOSs to suppress global flying noises, an above-IC graphene nano-electromechanical system (NEMS) switch and nano-crossbar array electrostatic discharge (ESD) protection structure, and graphene ESD interconnects. Full article
(This article belongs to the Special Issue Abridging the CMOS Technology)
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