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Intelligent IoT Circuits and Systems
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Intelligent IoT Circuits and Systems

A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Electronic Sensors".

Deadline for manuscript submissions: closed (30 April 2022) | Viewed by 18167

Special Issue Editors

Prof. Dr. Yongpan Liu

E-Mail Website
Guest Editor
Circuits and Systems Division, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China
Interests: embedded system; nonvolatile computing; electronics design automation and power/thermal aware VLSI design and test
Prof. Dr. Keni Qiu

E-Mail Website
Guest Editor
Information Engineering College, Capital Normal University, Beijing 100048, China
Interests: embedded systems; energy harvesting edge computing; nonvolatile memory; processing in memory
Prof. Dr. Mengying Zhao

E-Mail Website
Guest Editor
School of Computer Science and Technology, Shandong University, Qingdao 266237, China
Interests: computer architecture; embedded systems; nonvolatile memory; reconfigurable computing
Prof. Dr. Jingtong Hu

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, Swanson School of Engineering, University of Pittsburgh, Pittsburgh, PA 15261, USA
Interests: on-device AI; embedded systems; cyber-physical systems

Special Issue Information

Dear Colleagues,

The Internet of Things (IoT) is regarded as a very promising market in the next decade. However, batteries have become as a critical obstacle due to their limited operating time and frequent maintenance requirements. Energy harvesting and low-power techniques are proposed to relieve these problems, and self-powered sensor nodes are attracting increasing attention. Furthermore, the huge amount of data from sensors also poses a great challenge for bandwidth and processing capability of cloud technologies. Edge computing is also becoming widely used. Therefore, intelligent IoT circuits and systems have been explored from device, circuit, architecture, software, and system optimization aspects for various applications.

We invite manuscripts for this forthcoming Special Issue in all aspects pertinent to Intelligent IoT Circuits and Systems. Both reviews and original research articles are welcome. Reviews should provide an up-to-date and critical overview of state-of-the-art technologies such as nonvolatile computing, energy harvesting, edge computing, machine learning accelerators, and embedded software for intelligent IoT. Original research papers that describe the utilization of intelligent IoT circuits and systems are of interest. If you have suggestions that you would like to discuss beforehand, please feel free to contact us. We look forward to and welcome your participation in this Special Issue.

Prof. Dr. Yongpan Liu
Prof. Dr. Keni Qiu
Prof. Dr. Mengying Zhao
Prof. Dr. Jingtong Hu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Sensors is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Intelligent IoT
  • Nonvolatile computing
  • Energy harvesting
  • Edge computing
  • Machine learning accelerator
  • Embedded software

Published Papers (4 papers)

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Research

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15 pages, 8736 KiB  
Article
Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes
by Subin Kim and Jun-Eun Park
Sensors 2022, 22(11), 4284; https://0-doi-org.brum.beds.ac.uk/10.3390/s22114284 - 04 Jun 2022
Cited by 1 | Viewed by 2754
Abstract
This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored [...] Read more.
This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored data without charge loss issue. Hence, the PS-GC can offer unlimited retention time in the same manner as static RAM (SRAM). Due to the extended retention time, bulky capacitors in conventional eDRAM are no longer needed, thereby, improving the area efficiency of eDRAM-based analog PIMs. The active leakage compensation of the PS-GC can effectively hold stored data even in a deep-submicron process that show significant leakage current. Therefore, the PS-GC can accelerate write-access time and read-access time without concern of increased leakage current. The proposed gain cell and its 64 × 64 eDRAM macro were implemented in a 28 nm CMOS process. The bitcell of the proposed gain cell has 0.79- and 0.58-times the area of those of 6T SRAM and 8T STAM, respectively. The post-layout simulation results demonstrate that the eDRAM maintains the pseudo-static operation with unlimited retention time successfully under wide range variations of process, voltage and temperature. At the operating frequency of 667 MHz, the eDRAM macro achieved an operating voltage range from 0.9 to 1.2 V and operating temperature range from −25 to 85 °C regardless of the process variation. The post-layout simulated write-access time and read-access time were below 0.3 ns at an operating temperature of 85 °C. The PS-GC consumes a static power of 2.2 nW/bit at an operating temperature of 25 °C. Full article
(This article belongs to the Special Issue Intelligent IoT Circuits and Systems)
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10 pages, 2011 KiB  
Communication
Evaluation of HPC Acceleration and Interconnect Technologies for High-Throughput Data Acquisition
by Alessandro Cilardo
Sensors 2021, 21(22), 7759; https://0-doi-org.brum.beds.ac.uk/10.3390/s21227759 - 22 Nov 2021
Cited by 1 | Viewed by 1892
Abstract
Efficient data movement in multi-node systems is a crucial issue at the crossroads of scientific computing, big data, and high-performance computing, impacting demanding data acquisition applications from high-energy physics to astronomy, where dedicated accelerators such as FPGA devices play a key role coupled [...] Read more.
Efficient data movement in multi-node systems is a crucial issue at the crossroads of scientific computing, big data, and high-performance computing, impacting demanding data acquisition applications from high-energy physics to astronomy, where dedicated accelerators such as FPGA devices play a key role coupled with high-performance interconnect technologies. Building on the outcome of the RECIPE Horizon 2020 research project, this work evaluates the use of high-bandwidth interconnect standards, namely InfiniBand EDR and HDR, along with remote direct memory access functions for direct exposure of FPGA accelerator memory across a multi-node system. The prototype we present aims at avoiding dedicated network interfaces built in the FPGA accelerator itself, leaving most of the resources for user acceleration and supporting state-of-the-art interconnect technologies. We present the detail of the proposed system and a quantitative evaluation in terms of end-to-end bandwidth as concretely measured with a real-world FPGA-based multi-node HPC workload. Full article
(This article belongs to the Special Issue Intelligent IoT Circuits and Systems)
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19 pages, 3985 KiB  
Article
Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing
by Hsu-Yu Kao, Xin-Jia Chen and Shih-Hsu Huang
Sensors 2021, 21(15), 5081; https://0-doi-org.brum.beds.ac.uk/10.3390/s21155081 - 27 Jul 2021
Cited by 1 | Viewed by 2379
Abstract
Convolution operations have a significant influence on the overall performance of a convolutional neural network, especially in edge-computing hardware design. In this paper, we propose a low-power signed convolver hardware architecture that is well suited for low-power edge computing. The basic idea of [...] Read more.
Convolution operations have a significant influence on the overall performance of a convolutional neural network, especially in edge-computing hardware design. In this paper, we propose a low-power signed convolver hardware architecture that is well suited for low-power edge computing. The basic idea of the proposed convolver design is to combine all multipliers’ final additions and their corresponding adder tree to form a partial product matrix (PPM) and then to use the reduction tree algorithm to reduce this PPM. As a result, compared with the state-of-the-art approach, our convolver design not only saves a lot of carry propagation adders but also saves one clock cycle per convolution operation. Moreover, the proposed convolver design can be adapted for different dataflows (including input stationary dataflow, weight stationary dataflow, and output stationary dataflow). According to dataflows, two types of convolve-accumulate units are proposed to perform the accumulation of convolution results. The results show that, compared with the state-of-the-art approach, the proposed convolver design can save 15.6% power consumption. Furthermore, compared with the state-of-the-art approach, on average, the proposed convolve-accumulate units can reduce 15.7% power consumption. Full article
(This article belongs to the Special Issue Intelligent IoT Circuits and Systems)
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Review

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43 pages, 3065 KiB  
Review
A Comprehensive Review of Internet of Things: Technology Stack, Middlewares, and Fog/Edge Computing Interface
by Omer Ali, Mohamad Khairi Ishak, Muhammad Kamran Liaquat Bhatti, Imran Khan and Ki-Il Kim
Sensors 2022, 22(3), 995; https://0-doi-org.brum.beds.ac.uk/10.3390/s22030995 - 27 Jan 2022
Cited by 45 | Viewed by 9936
Abstract
The Internet of Things (IoT) is an extensive network of heterogeneous devices that provides an array of innovative applications and services. IoT networks enable the integration of data and services to seamlessly interconnect the cyber and physical systems. However, the heterogeneity of devices, [...] Read more.
The Internet of Things (IoT) is an extensive network of heterogeneous devices that provides an array of innovative applications and services. IoT networks enable the integration of data and services to seamlessly interconnect the cyber and physical systems. However, the heterogeneity of devices, underlying technologies and lack of standardization pose critical challenges in this domain. On account of these challenges, this research article aims to provide a comprehensive overview of the enabling technologies and standards that build up the IoT technology stack. First, a layered architecture approach is presented where the state-of-the-art research and open challenges are discussed at every layer. Next, this research article focuses on the role of middleware platforms in IoT application development and integration. Furthermore, this article addresses the open challenges and provides comprehensive steps towards IoT stack optimization. Finally, the interfacing of Fog/Edge Networks to IoT technology stack is thoroughly investigated by discussing the current research and open challenges in this domain. The main scope of this study is to provide a comprehensive review into IoT technology (the horizontal fabric), the associated middleware and networks required to build future proof applications (the vertical markets). Full article
(This article belongs to the Special Issue Intelligent IoT Circuits and Systems)
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