Energy, Area, and Speed—Efficient Digital Circuits

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Electrical, Electronics and Communications Engineering".

Deadline for manuscript submissions: closed (31 December 2021) | Viewed by 6256

Special Issue Editor


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Guest Editor
Department of Digital Systems, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland
Interests: logic synthesis; decomposition; technology mapping; cyber-physical systems; FPGA; CPLD
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Special Issue Information

Dear Colleagues,

The development of digital circuits makes research on logic synthesis issues extremely important. It is crucial to develop such methodologies for designing digital circuits that will provide solutions effective in terms of the number of resources used (Area), speed of operation (Speed), or ensuring low power consumption. Especially, design techniques associated with power consumption limitation have become extremely popular recently. These issues are extremely important in the area of programmable devices (FPGA, CPLD, and SoC). The problems of decomposition, technology mapping, coding of internal states, and many other issues are directly related to obtaining effective solutions. Of course, testing and validation are an inseparable element of the synthesis of digital circuits.

It is worth emphasizing that the rapid development of Cyber-Physical Systems (CPS) and the Internet of Things (IoT) also forces the development of effective techniques for designing these systems at the lowest level: the physical layer. Unfortunately, this aspect is often overlooked in many works on CPS. In this situation, the concept of the Synthesis of Cyber-Physical Systems appears, where the issues of system efficiency in terms of area; speed; and, in particular, power consumption are key. There are issues related to the effective implementation of measurement algorithms, data transmission issues, and effective motor control.

Of course, logic functions can be implemented in many ways. For industrial applications, the universal way to implement control functions is to use the Programmable Logic Controller (PLC). From this perspective, an effective digital system is an efficiently designed PLC that implements an effective control algorithm.

In this short introduction, only the outline of issues related to ‘’Energy, Area, Speed—Efficient Digital Circuits’’ is presented, which in the general case is much wider. I encourage authors who identify their work with this title to submit their work to the Special Issue, even if some issues are not explicitly mentioned here.

Dr. Marcin Kubica
Guest Editor

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Keywords

  • Logic synthesis
  • Decomposition
  • Technology mapping
  • Computer-aided design
  • Petri net-based systems
  • FPGA
  • CPLD
  • Programmable Logic Controller (PLC)
  • Cyber-physical systems (CPS)
  • Cyber-physical synthesis
  • CPS measuring systems
  • CPS digital motor control

Published Papers (3 papers)

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Research

27 pages, 3777 KiB  
Article
A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures
by Tomasz Garbolino
Appl. Sci. 2021, 11(20), 9476; https://0-doi-org.brum.beds.ac.uk/10.3390/app11209476 - 12 Oct 2021
Cited by 4 | Viewed by 2100
Abstract
Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as [...] Read more.
Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT-LFSR-TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed. Full article
(This article belongs to the Special Issue Energy, Area, and Speed—Efficient Digital Circuits)
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15 pages, 1395 KiB  
Article
Logic Synthesis Strategy Oriented to Low Power Optimization
by Marcin Kubica, Adam Opara and Dariusz Kania
Appl. Sci. 2021, 11(19), 8797; https://0-doi-org.brum.beds.ac.uk/10.3390/app11198797 - 22 Sep 2021
Cited by 8 | Viewed by 1711
Abstract
The article presents a synthesis strategy focused on low power implementations of combinatorial circuits in an array-type FPGA structure. Logic functions are described by means of BDD. A new form of the SWitch activity BDD diagram (SWBDD) is proposed, which enables a function [...] Read more.
The article presents a synthesis strategy focused on low power implementations of combinatorial circuits in an array-type FPGA structure. Logic functions are described by means of BDD. A new form of the SWitch activity BDD diagram (SWBDD) is proposed, which enables a function decomposition to minimize the switching activity of circuits. The essence of the proposed idea lies in the proper ordering of the variables and cutting the diagram, ensuring the minimization of switching in the combination circuit. This article contains the results of experiments confirming the effectiveness of the developed concept of decomposition. They were performed on popular benchmarks using academic and commercial synthesis systems. Full article
(This article belongs to the Special Issue Energy, Area, and Speed—Efficient Digital Circuits)
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13 pages, 385 KiB  
Article
Conversion between Logic and Algebraic Expressions of Boolean Control Networks
by Cailu Wang and Yuegang Tao
Appl. Sci. 2020, 10(20), 7180; https://0-doi-org.brum.beds.ac.uk/10.3390/app10207180 - 15 Oct 2020
Cited by 1 | Viewed by 1761
Abstract
The conversion between logic and algebraic expressions of Boolean control networks plays a worthy role in the analysis and design of digital circuits. In this paper, for a single Boolean function, a direct conversion between the minterm canonical form and the structure matrix [...] Read more.
The conversion between logic and algebraic expressions of Boolean control networks plays a worthy role in the analysis and design of digital circuits. In this paper, for a single Boolean function, a direct conversion between the minterm canonical form and the structure matrix is provided. For a Boolean control network consisting of systems of Boolean functions, two algorithms are developed to achieve the mutual conversion between the logic and algebraic expressions. The presented algorithms decrease exponentially the complexity of the semi-tensor product based method. Some numerical examples are given to demonstrate the algorithms and to compare our method with the existing ones. Full article
(This article belongs to the Special Issue Energy, Area, and Speed—Efficient Digital Circuits)
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