Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
4.5
2.7
Journals
Applied Sciences
Special Issues
New Aspects of Si-Based Material and Device
share announcement

New Aspects of Si-Based Material and Device

A special issue of Applied Sciences (ISSN 2076-3417). This special issue belongs to the section "Materials Science and Engineering".

Deadline for manuscript submissions: closed (30 September 2021) | Viewed by 35030

Special Issue Editor

Dr. Hyungjin Kim

E-Mail Website
Guest Editor
Department of Electronic Engineering, Inha University, Incheon 22212, Republic of Korea
Interests: CMOS/CMOS-compatible logic devices; emerging memory devices; processing-in-memory; neuromorphic system

Special Issue Information

Dear Colleagues,

For more than half a century, Si-based materials and devices have been utilized and mass-produced for a wide range of uses including microprocessors and memory technologies thanks to high-quality silicon dioxide and cost-effectiveness. Alternative semiconductor materials have been investigated to replace Si as the end of Moore’s law is approaching, however, it is still important to understand fundamental material properties of Si and develop Si-based devices in order to provide novel breakthrough approaches to overcome the physical limits of current ICs and present their feasibility with the mature Si technology platform. This special issue is devoted to highlight pioneering research papers, rapid communications, and review articles on Si-based materials and devices for advanced semiconductor technologies. The topics of interest of this special issue include, but are not necessarily limited to:

  • Si-based logic devices with steep switching characteristics
  • Si-based materials and processes for advanced CMOS technology
  • Si-based memory devices, array architectures and applications
  • Co-integration of emerging devices with Si CMOS circuitry
  • Amorphous and polycrystalline Si-based devices and applications
  • Si-based power devices and processes
  • Si-based photonics

Prof. Hyungjin Kim
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Applied Sciences is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Si-based logic devices with steep switching characteristics
  • Novel Si-based materials and processes for advanced CMOS technology
  • Si-based memory devices, array architectures and applications
  • Co-integration of emerging devices with Si CMOS circuitry
  • Amorphous and polycrystalline Si-based devices and applications
  • Si-based power electronics
  • Si-based photonics

Published Papers (7 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

Jump to: Review

10 pages, 3915 KiB  
Article
A Systematic Compact Model Parameter Calibration with Adaptive Pattern Search Algorithm
by Jeesoo Chang, Sungmin Hwang, Kyungchul Park, Taejin Jang, Kyung-Kyu Min, Min-Hye Oh, Jonghyuk Park, Jong-Ho Lee and Byung-Gook Park
Appl. Sci. 2021, 11(9), 4155; https://0-doi-org.brum.beds.ac.uk/10.3390/app11094155 - 01 May 2021
Cited by 2 | Viewed by 1914
Abstract
A systematic device-model calibration (extraction) methodology has been proposed to reduce parameter calibration time of advanced compact model for modern nano-scale semiconductor devices. The adaptive pattern search algorithm is a variant of the direct search method, which explore in the parameter space with [...] Read more.
A systematic device-model calibration (extraction) methodology has been proposed to reduce parameter calibration time of advanced compact model for modern nano-scale semiconductor devices. The adaptive pattern search algorithm is a variant of the direct search method, which explore in the parameter space with adaptive searching step and direction. It is very straightforward, but powerful, in high dimensional optimization problem since adaptive step and direction are decided by simple computation. The proposed method iterates less but shows superior accuracy over the conventional method. It is possible to be applied to a behavioral or empirical model correspond to emerging devices, such as tunneling field-effect transistor (TFET) and negative capacitance field-effect transistor (NCFET) due to its universality in parameter calibration for the model accuracy. Full article
(This article belongs to the Special Issue New Aspects of Si-Based Material and Device)
►▼ Show Figures

Figure 1

10 pages, 2556 KiB  
Article
Quantized Weight Transfer Method Using Spike-Timing-Dependent Plasticity for Hardware Spiking Neural Network
by Sungmin Hwang, Hyungjin Kim and Byung-Gook Park
Appl. Sci. 2021, 11(5), 2059; https://0-doi-org.brum.beds.ac.uk/10.3390/app11052059 - 25 Feb 2021
Cited by 3 | Viewed by 2206
Abstract
A hardware-based spiking neural network (SNN) has attracted many researcher’s attention due to its energy-efficiency. When implementing the hardware-based SNN, offline training is most commonly used by which trained weights by a software-based artificial neural network (ANN) are transferred to synaptic devices. However, [...] Read more.
A hardware-based spiking neural network (SNN) has attracted many researcher’s attention due to its energy-efficiency. When implementing the hardware-based SNN, offline training is most commonly used by which trained weights by a software-based artificial neural network (ANN) are transferred to synaptic devices. However, it is time-consuming to map all the synaptic weights as the scale of the neural network increases. In this paper, we propose a method for quantized weight transfer using spike-timing-dependent plasticity (STDP) for hardware-based SNN. STDP is an online learning algorithm for SNN, but we utilize it as the weight transfer method. Firstly, we train SNN using the Modified National Institute of Standards and Technology (MNIST) dataset and perform weight quantization. Next, the quantized weights are mapped to the synaptic devices using STDP, by which all the synaptic weights connected to a neuron are transferred simultaneously, reducing the number of pulse steps. The performance of the proposed method is confirmed, and it is demonstrated that there is little reduction in the accuracy at more than a certain level of quantization, but the number of pulse steps for weight transfer substantially decreased. In addition, the effect of the device variation is verified. Full article
(This article belongs to the Special Issue New Aspects of Si-Based Material and Device)
►▼ Show Figures

Figure 1

10 pages, 2081 KiB  
Article
Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure
by Garam Kim, Jang Hyun Kim, Jaemin Kim and Sangwan Kim
Appl. Sci. 2020, 10(15), 5378; https://0-doi-org.brum.beds.ac.uk/10.3390/app10155378 - 04 Aug 2020
Cited by 7 | Viewed by 3322
Abstract
Metal gate technology is one of the most important methods used to increase the low on-current of tunnel field-effect transistors (TFETs). However, metal gates have different work-functions for each grain during the deposition process, resulting in work-function variation (WFV) effects, which means that [...] Read more.
Metal gate technology is one of the most important methods used to increase the low on-current of tunnel field-effect transistors (TFETs). However, metal gates have different work-functions for each grain during the deposition process, resulting in work-function variation (WFV) effects, which means that the electrical characteristics vary from device to device. The WFV of a planar TFET, double-gate (DG) TFET, and electron-hole bilayer TFET (EHBTFET) were examined by technology computer-aided design (TCAD) simulations to analyze the influences of device structure and to find strategies for suppressing the WFV effects in TFET. Comparing the WFV effects through the turn-on voltage (Vturn-on) distribution, the planar TFET showed the largest standard deviation (σVturn-on) of 20.1 mV, and it was reduced by −26.4% for the DG TFET and −80.1% for the EHBTFET. Based on the analyses regarding metal grain distribution and energy band diagrams, the WFV of TFETs was determined by the number of metal grains involved in the tunneling current. Therefore, the EHBTFET, which can determine the tunneling current by all of the metal grains where the main gate and the sub gate overlap, is considered to be a promising structure that can reduce the WFV effect of TFETs. Full article
(This article belongs to the Special Issue New Aspects of Si-Based Material and Device)
►▼ Show Figures

Figure 1

7 pages, 3894 KiB  
Article
Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation
by Kitae Lee, Sihyun Kim, Daewoong Kwon and Byung-Gook Park
Appl. Sci. 2020, 10(14), 4977; https://0-doi-org.brum.beds.ac.uk/10.3390/app10144977 - 20 Jul 2020
Cited by 3 | Viewed by 3219
Abstract
Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (VDD) and power scaling limitations. Recently, wafer-level integrated tunneling-based ternary CMOS (TCMOS) has been successfully reported. However, the TCMOS requires [...] Read more.
Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (VDD) and power scaling limitations. Recently, wafer-level integrated tunneling-based ternary CMOS (TCMOS) has been successfully reported. However, the TCMOS requires large VDD (> 1 V), because a wide leakage region before on-current should be necessary to make the stable third voltage state. In this study, TCMOS consisting of ferroelectric-gate field effect transistors (FE-TCMOS) is proposed and its performance evaluated through 2-D technology computer-aided design (TCAD) simulations. As a result, it is revealed that the larger subthreshold swing and the steeper subthreshold swing are achievable by polarization switching in the ferroelectric layer, compared to conventional MOSFETs with high-k gate oxide, and thus the FE-TCMOS can have the more stable (larger static noise margin) ternary inverter operations at the lower VDD. Full article
(This article belongs to the Special Issue New Aspects of Si-Based Material and Device)
►▼ Show Figures

Figure 1

9 pages, 3487 KiB  
Article
Rigorous Study on Hump Phenomena in Surrounding Channel Nanowire (SCNW) Tunnel Field-Effect Transistor (TFET)
by Seung-Hyun Lee, Jeong-Uk Park, Garam Kim, Dong-Woo Jee, Jang Hyun Kim and Sangwan Kim
Appl. Sci. 2020, 10(10), 3596; https://0-doi-org.brum.beds.ac.uk/10.3390/app10103596 - 22 May 2020
Cited by 6 | Viewed by 2578
Abstract
In this paper, analysis and optimization of surrounding channel nanowire (SCNW) tunnel field-effect transistor (TFET) has been discussed with the help of technology computer-aided design (TCAD) simulation. The SCNW TFET features an ultra-thin tunnel layer at source sidewall and shows a high on [...] Read more.
In this paper, analysis and optimization of surrounding channel nanowire (SCNW) tunnel field-effect transistor (TFET) has been discussed with the help of technology computer-aided design (TCAD) simulation. The SCNW TFET features an ultra-thin tunnel layer at source sidewall and shows a high on-current (ION). In spite of the high electrical performance, the SCNW TFET suffers from hump effect which deteriorates subthreshold swing (S). In order to solve the issue, an origin of hump effect is analyzed firstly. Based on the simulation, the transfer curve in SCNW TFET is decoupled into vertical- and lateral-BTBTs. In addition, the lateral-BTBT causes the hump effect due to low turn-on voltage (VON) and low ION. Therefore, the device design parameter is optimized to suppress the hump effect by adjusting thickness of the ultra-thin tunnel layer. Finally, we compared the electrical properties of the planar, nanowire and SCNW TFET. As a result, the optimized SCNW TFET shows better electrical performance compared with other TFETs. Full article
(This article belongs to the Special Issue New Aspects of Si-Based Material and Device)
►▼ Show Figures

Figure 1

9 pages, 3747 KiB  
Article
Analysis on Tunnel Field-Effect Transistor with Asymmetric Spacer
by Hyun Woo Kim and Daewoong Kwon
Appl. Sci. 2020, 10(9), 3054; https://0-doi-org.brum.beds.ac.uk/10.3390/app10093054 - 27 Apr 2020
Cited by 6 | Viewed by 3059
Abstract
Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously. In order to analyze the proposed Tunnel FET, electrical characteristics are evaluated by technology computer-aided design (TCAD) simulations with calibrated tunneling model parameters. The [...] Read more.
Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously. In order to analyze the proposed Tunnel FET, electrical characteristics are evaluated by technology computer-aided design (TCAD) simulations with calibrated tunneling model parameters. The impact of the spacer κ values on tunneling rate is investigated with the symmetric spacer. As the κ values of the spacer increase, the on-current becomes enhanced since tunneling probabilities are increased by the fringing field through the spacer. However, on the drain-side, that fringing field through the drain-side spacer increases ambipolar current and gate-to-drain capacitance, which degrades leakage property and switching response. Therefore, the drain-side low-κ spacer, which makes the low fringing field, is adapted asymmetrically with the source-side high-κ spacer. This asymmetric spacer results in the reduction of gate-to-drain capacitance and switching delay with the improved on-current induced by the source-side high-κ spacer. Full article
(This article belongs to the Special Issue New Aspects of Si-Based Material and Device)
►▼ Show Figures

Figure 1

Review

Jump to: Research

18 pages, 10014 KiB  
Review
Architecture and Process Integration Overview of 3D NAND Flash Technologies
by Geun Ho Lee, Sungmin Hwang, Junsu Yu and Hyungjin Kim
Appl. Sci. 2021, 11(15), 6703; https://0-doi-org.brum.beds.ac.uk/10.3390/app11156703 - 21 Jul 2021
Cited by 38 | Viewed by 17637
Abstract
In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND [...] Read more.
In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry and academia and adopted in commercial mass production. In this paper, 3D NAND flash technologies are reviewed in terms of their architecture and fabrication methods, and the advantages and disadvantages of the architectures are compared. Full article
(This article belongs to the Special Issue New Aspects of Si-Based Material and Device)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-7
Back to TopTop