Research

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14 pages, 7436 KiB

Open AccessFeature PaperArticle

A 96 dB DR Second-Order CIFF Delta-Sigma Modulator with Rail-to-Rail Input Voltage Range

by Juncheol Kim, Neungin Jeon, Wonkyu Do, Euihoon Jung, Hongjin Kim, Hojin Park and Young-Chan Jang

Electronics 2024, 13(6), 1084; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics13061084 - 15 Mar 2024

Viewed by 581

Abstract

A second-order delta-sigma modulator (DSM) is proposed for readout integrated circuits of sensor applications requiring a small area and low-power consumption. The proposed second-order CIFF DSM with the architecture of cascaded-of-integrator feedforward (CIFF) basically consists of two integrators, a 3-bit quantizer, data-weighted averaging [...] Read more.

A second-order delta-sigma modulator (DSM) is proposed for readout integrated circuits of sensor applications requiring a small area and low-power consumption. The proposed second-order CIFF DSM with the architecture of cascaded-of-integrator feedforward (CIFF) basically consists of two integrators, a 3-bit quantizer, data-weighted averaging (DWA) circuit, and clock generator. The use of the 3-bit quantizer instead of the single-bit quantizer reduces the size of the feedback capacitor in the first integrator. The 3-bit quantizer is designed based on a successive approximation register analog-to-digital converter for small area and low power implementation. Furthermore, the proposed second-order CIFF DSM has a single supply without an additional reference driver while having a wide analog input voltage range with rail to rail. The proposed second-order CIFF DSM, implemented using a 130 nm 1-poly 6-metal CMOS process with a supply of 1.5 V, has an area of 0.096 mm². It has a sampling frequency of 500 kHz for the implementation of an input bandwidth of 2 kHz and an oversampling ratio of 125. The measured peak signal-to-noise and distortion ratio is approximately 90 dB when the differential analog input signal has a frequency of 353 Hz and an amplitude of 1.2 Vpp. The measured dynamic range is approximately 96.3 dB. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits, Volume 2)

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16 pages, 2606 KiB

Open AccessArticle

An All-Digital Timing Mismatch Calibration Algorithm Based on Reference Channel for TIADC

by Wei Zhong, Yemin Dong, Lili Lang, Wei Xiong, Lin Sun, Yu Liu, Haijing Liu and Zhenwei Zhang

Electronics 2024, 13(6), 1058; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics13061058 - 12 Mar 2024

Viewed by 476

Abstract

This paper proposes an all-digital calibration algorithm that utilizes a reference channel to suppress the timing mismatch in the Time-Interleaved Analog-to-Digital Converter (TIADC). The output of the reference channel is aligned with each sub-channel in turn, therefore enabling the simultaneous sampling and conversion [...] Read more.

This paper proposes an all-digital calibration algorithm that utilizes a reference channel to suppress the timing mismatch in the Time-Interleaved Analog-to-Digital Converter (TIADC). The output of the reference channel is aligned with each sub-channel in turn, therefore enabling the simultaneous sampling and conversion of the same input signal. First, the statistical characteristics across the channels are employed for estimating the timing mismatch; then, by comparing the output difference between the reference channel and the sub-channels that are sampled simultaneously, the deviation of the derivator can be calibrated. Finally, combining both calibration results yields an accurate final output. This proposed algorithm provides an effective solution to improve TIADC performance in high-speed data acquisition systems. The proposed architecture is applied to a 12-bit 2.4 GS/s four-channel TIADC model, and then its effectiveness is verified. The simulation results exhibit that the Effective Number Of Bits (ENOB) at an input signal frequency of 984 MHz shows a remarkable improvement from 6.88 bits to 11.92 bits. The effectiveness of this technique is also demonstrated through the off-chip calibration of a commercial 12-bit four-channel 2 GS/s TIADC using a 680 MHz input signal that is based on the actual chip results. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits, Volume 2)

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21 pages, 3803 KiB

Open AccessArticle

A Fast Mismatch Calibration Method Based on Frequency Domain Orthogonal Decomposition for Time-Interleaved Analog-to-Digital Converters

by Lin Sun, Lili Lang, Wei Zhong, Haijing Liu and Yemin Dong

Electronics 2023, 12(24), 5042; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics12245042 - 18 Dec 2023

Cited by 2 | Viewed by 615

Abstract

This paper proposes a fully digital background calibration method for time-interleaved analog-to-digital converter (TIADC) mismatches. The method analyzes the frequency and phase of spurious signals caused by three types of mismatches in TIADCs in the frequency domain. By utilizing the Hilbert transform and [...] Read more.

This paper proposes a fully digital background calibration method for time-interleaved analog-to-digital converter (TIADC) mismatches. The method analyzes the frequency and phase of spurious signals caused by three types of mismatches in TIADCs in the frequency domain. By utilizing the Hilbert transform and frequency shifting, orthogonal basis signals located at the mismatch frequencies can be constructed. The calibration of mismatches is achieved by linearly combining the orthogonal basis signals with the estimated coefficients and subtracting them from the original signal. The estimation of coefficients is determined by evaluating the correlation between the linear combination of orthogonal basis signals and the calibrated signal. Furthermore, an exponential moving average (EMA) and least mean square (LMS) algorithm are introduced to expedite the coefficient estimation process. The entire calibration process converges in merely 600 samples, significantly improving the convergence speed. By monitoring the amplitude of the input signal and adjusting the LMS step, the algorithm is functional under different amplitude signals, enhancing the robustness. An off-chip calibration is conducted based on a commercial 14-bit, 8-channel, 2.4GSPS TIADC. Results indicate that all spurious signals are suppressed below 80 dB, and the convergence rate is consistent with the simulation. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits, Volume 2)

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13 pages, 2277 KiB

Open AccessCommunication

A 22.3-Bit Third-Order Delta-Sigma Modulator for EEG Signal Acquisition Systems

by Qianqian Wang, Fei Liu, Liyin Fu, Qianhui Li, Jing Kang, Ke Chen and Zongliang Huo

Electronics 2023, 12(23), 4866; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics12234866 - 02 Dec 2023

Viewed by 685

Abstract

This paper presents a high resolution delta-sigma modulator for continuous acquisition of electroencephalography (EEG) signals. The third-order single-loop architecture with a 1-bit quantizer is adopted to achieve 22.3-bit resolution. The effects of thermal noise on the performance of the delta-sigma modulator are analyzed [...] Read more.

This paper presents a high resolution delta-sigma modulator for continuous acquisition of electroencephalography (EEG) signals. The third-order single-loop architecture with a 1-bit quantizer is adopted to achieve 22.3-bit resolution. The effects of thermal noise on the performance of the delta-sigma modulator are analyzed to reasonably allocate the switched-capacitor sizes for optimal signal to noise ratio (SNR) and minimum chip area. The coefficients in feedback path and input path are optimized to avoid the signal distortion under the full-scale input voltage range with almost no increase in total capacitance sizes. Fabricated in 0.5 µm CMOS technology and powered by a 5 V voltage supply, the proposed delta-sigma modulator can achieve 136 dB peak SNR with 16 Hz input and 137 dB dynamic range in 100 Hz signal bandwidth with an oversampling ratio of 512. The modulator dissipates 700 µA. The core chip area is 1.96 mm

^{2}

. The modulator occupies 1.41 mm

^{2}

and the decimator occupies 0.55 mm

^{2}

. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits, Volume 2)

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11 pages, 436 KiB

Open AccessArticle

Python Framework for Modular and Parametric SPICE Netlists Generation

by Sergio Vinagrero Gutiérrez, Giorgio Di Natale and Elena-Ioana Vatajelu

Electronics 2023, 12(18), 3970; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics12183970 - 20 Sep 2023

Viewed by 944

Abstract

Due to the complex specifications of current electronic systems, design decisions need to be explored automatically. However, the exploration process is a complex task given the plethora of design choices such as the selection of components, number of components, operating modes of each [...] Read more.

Due to the complex specifications of current electronic systems, design decisions need to be explored automatically. However, the exploration process is a complex task given the plethora of design choices such as the selection of components, number of components, operating modes of each of the components, connections between the components and variety of ways in which the same functionality can be implemented. To tackle these issues, scripts are used to generate designs based on high-level abstract constructions. Still, this approach is usually ad hoc and platform dependent, making the whole procedure hardly reusable, scalable and versatile. We propose a generic, open-source framework tackling rapid design exploration for the generation of modular and parametric electronic designs that is able to work on any major simulator. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits, Volume 2)

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20 pages, 11679 KiB

Open AccessArticle

Design of Self-Calibration Comparator for 12-Bit SAR ADCs

by Junlong Tang, Yaodong Wang, Hongbo Gu and Wanghui Zou

Electronics 2023, 12(10), 2277; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics12102277 - 18 May 2023

Cited by 1 | Viewed by 2616

Abstract

A novel self-calibration comparator for a 12-bit 2.5 MSPS successive approximation register analog-to-digital converter (SAR ADC) applied in a touch microcontroller unit (MCU) with small area, high precision, fast response speed, and low-voltage detection is proposed in this paper. A combination of input/output [...] Read more.

A novel self-calibration comparator for a 12-bit 2.5 MSPS successive approximation register analog-to-digital converter (SAR ADC) applied in a touch microcontroller unit (MCU) with small area, high precision, fast response speed, and low-voltage detection is proposed in this paper. A combination of input/output offset storage (IOS/OOS) and an offset trimming circuit was employed to reduce the offset of the cascade preamplifier and the operational transconductance amplifier (OTA), a novel offset trimming circuit with a 5-bit digital controller was designed to further reduce the residual offset voltage, and an improved self-calibration technology was also implemented to compensate the conversion error in SAR ADC system to a minimum. Simulation and measured results show that the input-referred offset calibrating range is ±9.15 mV at 0.61 mV/step, the low-voltage detection of SAR ADC is realized by compensating the conversion error to a minimum, and the effective number of bits (ENOB) and figure of merit (FoM) at 5 V supply and 2.5 M/s rate in the 12-bit SAR ADC with a 95 nm CMOS are 11.33 bits and 726.6 fJ/conversion-step, respectively. The proposed self-calibration comparator applied in the SAR ADC system can automatically eliminate the offset voltage caused by nonidealities and meet the requirements of the touch MCU. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits, Volume 2)

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12 pages, 3230 KiB

Open AccessArticle

A Low-Power, Fully Integrated SC DC–DC Step-Up Converter with Phase-Reduced Soft-Charging Technique for Fully Implantable Neural Interfaces

by Sangmin Song, Minsung Kim and Sung-Yun Park

Electronics 2022, 11(22), 3659; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11223659 - 09 Nov 2022

Cited by 1 | Viewed by 2071

Abstract

We present a high-power conversion efficiency (PCE) on-chip switched-capacitor (SC) DC–DC step-up converter for a fully implantable neural interface operating with less than a few tens µW from energy harvesting. To improve the PCE in such light loads and wide variations of voltage-conversion [...] Read more.

We present a high-power conversion efficiency (PCE) on-chip switched-capacitor (SC) DC–DC step-up converter for a fully implantable neural interface operating with less than a few tens µW from energy harvesting. To improve the PCE in such light loads and wide variations of voltage-conversion ratio (VCR), which is a typical scenario for ultra-low-power fully implantable systems depending on energy harvesting, a phase-reduced soft-charging technique has been implemented in a step-up converter, thereby achieving very low VCR-sensitive PCE variation compared with other state-of-the-art works. The proposed DC–DC converter has been fabricated in a standard 180 nm CMOS 1P6M process. It exhibits high PCE (~80%) for wide input and output ranges from 0.5 V to 1.2 V and from 1.2 V to 1.8 V, respectively, with switching frequencies of 0.3–2 MHz, achieving a peak efficiency of 82.6% at 54 µW loads. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits, Volume 2)

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16 pages, 4936 KiB

Open AccessArticle

A Comparison of Off-Chip Differential and LC Input Matching Baluns in a Wideband and Low-Power RF-to-BB Current-Reuse Receiver Front-End

by Arash Abbasi and Frederic Nabki

Electronics 2022, 11(21), 3527; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11213527 - 29 Oct 2022

Viewed by 1275

Abstract

A wideband and low-power RF-to-baseband (BB) current-reuse receiver (CRR) front-end is proposed, and its performance is verified using two matching networks, one with an LC balun and on-chip biasing inductor, CRR1, and another with a differential balun and without on-chip biasing inductor, CRR2, [...] Read more.

A wideband and low-power RF-to-baseband (BB) current-reuse receiver (CRR) front-end is proposed, and its performance is verified using two matching networks, one with an LC balun and on-chip biasing inductor, CRR1, and another with a differential balun and without on-chip biasing inductor, CRR2, requiring less area. The transimpedance amplifier (TIA) and low-noise transconductance amplifier (LNTA) share the bias current from a single supply to reduce power consumption. It employs both an active-inductor (AI) and a

1 / f

noise-cancellation technique to improve the NF and RF bandwidth performance. A passive mixer is utilized for RF to BB conversion, which does not require any DC power and voltage headroom. Both CRR1 and CRR2 are fabricated in TSMC

130 n m

CMOS technology on a single die and packaged using a QFN48. CRR1 occupies an active area of 0.54

{mm}^{2}

. From 1 to

1.7

G

Hz

, it achieves a conversion gain of

41.5

d

B

, a double-sideband (DSB) NF of

6.5

d

B

,

S_{11} <

- 10

d

B

, and an IIP3 of

- 28.2

d

Bm

, while the local-oscillator (LO) frequency is at

1.3

G

Hz

. CRR2 occupies an active area of 0.025

{mm}^{2}

. From 0.2 to 1

G

Hz

, it achieves an average conversion gain of 37

d

B

, an average DSB NF of 8

d

B

, and an IIP3 of

- 21.5

d

Bm

while the LO frequency is at

0.7

G

Hz

. Both CRR1 and CRR2 consume

1.66

m A

from a

1.2

V

supply voltage. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits, Volume 2)

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Review

Jump to: Research

35 pages, 5622 KiB

Open AccessReview

A Review of Optical Sensors in CMOS

by Rodrigo Gounella, Gabriel M. Ferreira, Marcio L. M. Amorim, João Navarro Soares, Jr. and João Paulo Carmo

Electronics 2024, 13(4), 691; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics13040691 - 08 Feb 2024

Viewed by 1106

Abstract

This paper presents an overview of silicon-based optical sensors for the measurement of light in the visible spectrum range. The review is focused on sensors based on CMOS (complementary metal-oxide semiconductor) technology due to the high availability, low cost, ease of prototyping, and [...] Read more.

This paper presents an overview of silicon-based optical sensors for the measurement of light in the visible spectrum range. The review is focused on sensors based on CMOS (complementary metal-oxide semiconductor) technology due to the high availability, low cost, ease of prototyping, and well-established fabrication processes. CMOS technology allows integration with the CMOS readout and control electronics in the same microdevice, featuring high-volume fabrication with high-reproducibility and low-cost. This review starts with an explanation of the phenomena behind opto-electronic transduction. It also presents and describes the most common components responsible for optical transduction, readout electronics, and their main characteristics. This review finishes with the presentation of selected applications to grasp where and how these sensors can be used. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits, Volume 2)

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