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Design of Mixed Analog/Digital Circuits

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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (28 February 2022) | Viewed by 29380

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Special Issue Editors

Dr. João Paulo Pereira do Carmo

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Guest Editor

São Carlos School of Engineering (EESC), Department of Electrical Engineering (SEL), University of São Paulo (USP), São Carlos 13566-590, Brazil
Interests: analog and digital integrated circuits; micromachining and micro/nanofabrication technologies for mixed-mode/RF systems; solid-state integrated sensors; microactuators and microsystems; micro/nanodevices for industrial and biomedical applications; wireless systems for sensors and actuators; optical sensors and actuators; material technology for microsystems; microprocessor/microcomputer-based instrumentation and data-acquisition systems
Special Issues, Collections and Topics in MDPI journals

Prof. Dr. Subhanshu Gupta

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Guest Editor

Systems-on-Chip Lab, School of Electrical Engineering & Computer Science, University of Washington, Seattle, WA 98105, USA
Interests: centered around analog mixed-signal circuits and systems for wideband reconfigurable radio transceivers; signal and image processing paradigms; ultra-low-power energy harvesting circuits

Prof. Dr. Kunhee Cho

E-Mail Website
Guest Editor

School of Electronics Engineering, Kyungpook National University, Daegu 41566, Republic of Korea
Interests: power management integrated circuits; DC-DC converter; battery charger integrated circuits; power amplifiers

Special Issue Information

Dear Colleagues,

Since the invention of the transistor in 1948, the industry of semiconductors grown extensively. The existence of a modern world without electronic devices is unthinkable. According to IC Insights, a leading semiconductor market research company, the value of the 10 semiconductor sale leaders (including the foundries) in first quarter of 2020 was about $71 billion. This mark outperforms the $62.4 billion of the 20 semiconductor sales leaders in the same quarter of 2016, representing a growth of 4.47% per year. This indicator confirms that the industry of semiconductors is still very dynamic, offering both new technologies and new devices for new applications.

Everyday, new contributions of digital and analog circuits are published worldwide. For example, digital circuits are applied on FFT processors, digital signal processors, machine states, digital controllers, communication encoders/decoders, and random number generators. Additionally, analog circuits have found applications in data converters, amplifiers, filters, and multiplexers. For each type of circuit, the demand for energy-efficient solutions is more important in the context of mobile and autonomous devices in order to maximize the useful life of batteries.

This Special Issue invites new works, reviews, and innovative applications of mixed analog/digital circuits. Applications based on heterogeneous integration are also welcomed.

Prof. Dr. João Paulo Pereira do Carmo
Prof. Dr. Subhanshu Gupta
Prof. Dr. Kunhee Cho
Guest Editors

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

mixed analog/digital circuits design
optimization
applications
heterogeneous integration

Published Papers (10 papers)

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Research

16 pages, 1758 KiB

Open AccessArticle

A Design Methodology for Wideband Current-Reuse Receiver Front-Ends Aimed at Low-Power Applications

by Arash Abbasi and Frederic Nabki

Electronics 2022, 11(9), 1493; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11091493 - 06 May 2022

Cited by 3 | Viewed by 1573

Abstract

This work gives a design perspective on low-power and wideband RF-to-Baseband current-reuse receivers (CRR). The proposed CRR architecture design shares a single supply and biasing current among both LNTA and baseband circuits to reduce power consumption. The work discusses topology selection and a suitable design procedure of the low noise transconductance amplifier (LNTA), down-conversion passive-mixer, active-inductor (AI) and TIA circuits. Layout considerations are also discussed. The receiver was simulated in 130

n

m

CMOS technology and occupies an active area of 0.025

{mm}^{2}

. It achieves a wideband input matching of less than

- 10

d

B

from

0.8

G

Hz

3.4

G

Hz

. A conversion-gain of

39.5

d

B

, IIP3 of

- 28

d

Bm

and a double-sideband (DSB) NF of

5.6

d

B

is simulated at a local-oscillator (LO) frequency of

2.4

G

Hz

and an intermediate frequency (IF) of 10

M

Hz

, while consuming

1.92

mA from a

1.2

V

supply. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits)

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12 pages, 702 KiB

Open AccessArticle

A 4-Channel Ultra-Low Power Front-End Electronics in 65 nm CMOS for ATLAS MDT Detectors

by Syed Adeel Ali Shah, Marcello De Matteis, Hubert Kroha, Markus Fras, Oliver Kortner, Robert Richter and Andrea Baschirotto

Electronics 2022, 11(7), 1001; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11071001 - 24 Mar 2022

Viewed by 1502

Abstract

A 4-channel front-end electronics (4 × FEE) system for the muon drift tube in the ATLAS detector in the High-Luminosity LHC is presented. The overall channel architecture is optimized to reduce the power and area of the design. Each channel comprises a charge-sensitive preamplifier (CSP), shaper, discriminator and differential low-voltage signaling drivers. The proposed channel operates with a 5–100 fC input charge and exhibits a linear sensitivity of 8 mV/fC for the entire input charge range. The peaking time delay of the analog channel is 14.6 ns. At the output, the time representation of the input signal is provided in terms of the CMOS level and in scalable low-voltage signal (SLVS). The FEE consumes a current of 10.6 mA per channel from a single 1.2 V supply voltage. The full 4 × FEE design is realized in TSMC 65 nm CMOS technology and its die-area is 2 mm × 2 mm. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits)

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24 pages, 9512 KiB

Open AccessFeature PaperArticle

Low-Noise Amplifier for Deep-Brain Stimulation (DBS)

by Tiago Matheus Nordi, Rodrigo Henrique Gounella, Maximiliam Luppe, João Navarro Soares Junior, Erich Talamoni Fonoff, Eduardo Colombari, Murilo Araujo Romero and João Paulo Pereira do Carmo

Electronics 2022, 11(6), 939; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11060939 - 17 Mar 2022

Cited by 6 | Viewed by 6132

Abstract

Deep-brain stimulation (DBS) is an emerging research topic aiming to improve the quality of life of patients with brain diseases, and a great deal of effort has been focused on the development of implantable devices. This paper presents a low-noise amplifier (LNA) for the acquisition of biopotentials on DBS. This electronic module was designed in a low-voltage/low-power CMOS process, targeting implantable applications. The measurement results showed a gain of 38.6 dB and a −3 dB bandwidth of 2.3 kHz. The measurements also showed a power consumption of 2.8 μW. Simulations showed an input-referred noise of 6.2 μV_RMS. The LNA occupies a microdevice area of 122 μm × 283 μm, supporting its application in implanted systems. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits)

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20 pages, 5277 KiB

Open AccessFeature PaperArticle

A 28 nm Bulk CMOS Fully Digital BPSK Demodulator for US-Powered IMDs Downlink Communications

by Andrea Ballo, Alfio Dario Grasso and Marco Privitera

Electronics 2022, 11(5), 698; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11050698 - 24 Feb 2022

Cited by 5 | Viewed by 2614

Abstract

Low-invasive and battery-less implantable medical devices (IMDs) have been increasingly emerging in recent years. The developed solutions in the literature often concentrate on the Bidirectional Data-Link for long-term monitoring devices. Indeed, their ability to collect data and communicate them to the external world, namely Data Up-Link, has revealed a promising solution for bioelectronic medicine. Furthermore, the capacity to control organs such as the brain, nerves, heart-beat and gastrointestinal activities, made up through the manipulation of electrical transducers, could optimise therapeutic protocols and help patients’ pain relief. These kinds of stimulations come from the modulation of a powering signal generated from an externally placed unit coupled to the implanted receivers for power/data exchanging. The established communication is also defined as a Data Down-Link. In this framework, a new solution of the Binary Phase-Shift Keying (BPSK) demodulator is presented in this paper in order to design a robust, low-area, and low-power Down-Link for ultrasound (US)-powered IMDs. The implemented system is fully digital and PLL-free, thus reducing area occupation and making it fully synthesizable. Post-layout simulation results are reported using a 28 nm Bulk CMOS technology provided by TSMC. Using a 2 MHz carrier input signal and an implant depth of 1 cm, the data rate is up to 1.33 Mbit/s with a 50% duty cycle, while the minimum average power consumption is cut-down to 3.3 μW in the typical corner. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits)

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11 pages, 3183 KiB

Open AccessArticle

A New Realization of Electronically Tunable Multiple-Input Single-Voltage Output Second-Order LP/BP Filter Using VCII

by Leila Safari, Gianluca Barile, Giuseppe Ferri, Mattia Ragnoli and Vincenzo Stornelli

Electronics 2022, 11(4), 646; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11040646 - 18 Feb 2022

Cited by 10 | Viewed by 1501

Abstract

In this paper, a new realization of electronically tunable voltage output second-order low-pass (LP) and band-pass (BP) filter is presented. The circuit has a multiple-input single-output structure, and LP and BP outputs are provided using the same structure. One electronically variable second-generation voltage conveyor (VCII), whose impedance at the Y port can be electronically varied using a control current (I_con), two capacitors, and one resistor are used. By changing the value of I_con, the impedance value at the Y port can be electronically varied; therefore, the value of ω₀ can be tuned. This feature helps to reduce the number of passive components used. Interestingly, the LP and BP outputs are provided at the low-impedance Z port of the VCII, and there is no need for an extra voltage buffer for practical use. The circuit enjoys a simple realization consisting of only 24 MOS transistors. Simulation results using PSpice and 0.18 μm CMOS parameters are provided. The value of ω₀ can be varied from 1.2 MHz to 1.7 MHz, while I_con varies from 0 to 50 µA, with a power consumption variation from 244 µW to 515 µW. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits)

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9 pages, 2561 KiB

Open AccessArticle

A Flash Frequency Tuning Technique for SC-Based mm Wave VCOs

by Alessandro Parisi, Andrea Cavarra, Alessandro Finocchiaro, Giuseppe Papotto and Giuseppe Palmisano

Electronics 2022, 11(3), 433; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11030433 - 31 Jan 2022

Viewed by 1693

Abstract

This paper presents a flash frequency tuning technique for switched-capacitor-based, voltage-controlled oscillators operating at mm wave frequencies. The proposed strategy exploits a capacitor array and a small varactor for coarse and fine tuning, respectively, which are simultaneously operated thanks to a flash A/D-based control circuit. This avoids additional delay in the frequency calibration, thus enabling very fast-frequency locking operation. The VCO was fabricated in a 28 nm FD-SOI CMOS technology and provides an oscillation frequency around 39 GHz with an overall tuning range of 3.3 GHz. The circuit dissipates 8.4 mW from a power supply as low as 0.7 V, while occupying a silicon area of 210 µm × 150 µm. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits)

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19 pages, 6233 KiB

Open AccessArticle

A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator

by Neeru Agarwal, Neeraj Agarwal, Chih-Wen Lu and Masahito Oh-e

Electronics 2021, 10(18), 2257; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10182257 - 14 Sep 2021

Cited by 1 | Viewed by 3282

Abstract

A chopper-embedded bandgap reference (BGR) scheme is presented using 0.18 μm CMOS technology for low-frequency noise suppression in the clock generator application. As biasing circuitry produces significant flicker noise, along with thermal noise from passive components, the proposed low-noise chopper-stabilized BGR circuit was designed and implemented for a wide range of temperature from −40 to 125 °C, including a startup and self-biasing circuit to reduce critical low-frequency noise from the bias circuitry and op amp input offset voltage. The BGR circuit generated a reference voltage of 1.25 V for a supply voltage range of 2.5–3.3 V. The gain of the implemented BGR operational transconductance amplifier is 84.1 dB. A non-overlapping clock circuit was implemented to reduce the clock skew effect, which is also one of the noise contributors. The noise analysis of a chopped bandgap voltage reference was evaluated through cadence periodic steady-state (PSS) analysis and periodic noise (PNoise) analysis. The low-frequency flicker noise was reduced from 1.5 to 0.4 μV/sqrt(Hz) at 1 KHz, with the proposed chopping scheme in the bandgap. Comparisons of the noise performance of the chopper-embedded BGR, with and without a low-pass filter, were also performed, and the results show a further reduction in the overall noise. A reduction in the flicker noise, from 181.3 to 10.26 mV/sqrt(Hz) at 100 KHz, was observed with the filter. All circuit blocks of the proposed BGR scheme were designed and simulated using the EDA tool HSPICE, and layout generation was carried out by Laker. The BGR architecture layout dimensions are 285.25 μm × 125.38 μm. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits)

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16 pages, 5490 KiB

Open AccessArticle

An Area- and Energy-Efficient 16-Channel, AC-Coupled Neural Recording Analog Frontend for High-Density Multichannel Neural Recordings

by Hyeon-June Kim, Younghoon Park, Kyungsik Eom and Sung-Yun Park

Electronics 2021, 10(16), 1972; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10161972 - 16 Aug 2021

Cited by 4 | Viewed by 2491

Abstract

We present an AC-coupled modular 16-channel analog frontend with 1.774 fJ/c-s∙mm² energy- and area-product for a multichannel recording of broadband neural signals including local field potentials (LFPs) and extracellular action potentials (EAPs). To achieve such a small area- and energy-product, we employed an operational transconductance amplifier (OTA) with local positive feedback, instead of a widely-used folded cascode OTA (FC-OTA) or current mirror OTA for conventional neural recordings, while optimizing the design parameters affecting performance, power, and area trade-offs. In addition, a second pole was strategically introduced in the LNA to reduce the noise bandwidth without an in-channel low-pass filter. Compared to conventional works, the presented method shows better performance in terms of noise, power, and area usages. The performance of the fabricated 16-channel analog frontend is fully characterized in a benchtop and an in vitro setup. The 16-channel frontend embraces LFPs and EAPs with 4.27 μV_rms input referred noise (0.5–10 kHz) and 53.17 dB dynamic range, consuming 3.44 μW and 0.012 mm² per channel. The channel figure of merit (FoM) of the prototype is 147.87 fJ/c-s and the energy-area FoM (E-A FoM) is 1.774 fJ/c-s∙mm². Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits)

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17 pages, 20052 KiB

Open AccessArticle

A 33 MHz Fast-Locking PLL with Programmable VCO and Automatic Band Selection for Clock Generator Application

by Neeraj Agarwal, Neeru Agarwal, Chih-Wen Lu and Masahito Oh-e

Electronics 2021, 10(14), 1743; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10141743 - 20 Jul 2021

Cited by 1 | Viewed by 4033

Abstract

This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO) gain stage with automatic band selection. We successfully reduce the VCO gain (Kvco) and retain the desired frequency band. The proposed PLL comprises a prescaler, phase frequency detector (PFD), charge pump (CP), programmable VCO and automatic band selection circuit. The PLL prototype with all subblocks was implemented using the TSMC 0.18 μm 1P6M process. Contrary to conventional PLL architectures, the proposed architecture incorporates a real-time check and automatic band selection circuit in the secondary loop. A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit. A suitable way to maintain the Kvco low is to use multiple discrete frequency bands to accommodate the required frequency range. To maintain a low Kvco and fast locking, the automatic frequency band selection circuit also has two indigenous, most probable voltage levels. The proposed architecture provides the flexibility of not only band hopping but also band twisting to obtain an optimized Kvco for the desired output range, with the minimum jitter and spurs. The proposed programmable VCO was designed using a voltage-to-current-converter circuit and current DAC followed by a four-stage differential ring oscillator with a cross-coupled pair. The VCO frequency output range is 150–400 MHz, while the input frequency is 25 MHz. A sequential phase detection loop with a negligible dead zone was designed to adjust fine phase errors between the reference and feedback clocks. All circuit blocks of the proposed PLL were simulated using the EDA tool HSPICE and layout generation by Laker. The simulation and measured results of the proposed PLL show high linearity, with a dead zone of less than 10 pV. The differential VCO was used to improve the linearity and phase noise of the PLL. The chip measured results show rms jitter of 19.10 ps. The PLL prototype also has an additional safety feature of a power down mode. The automatic band selection PLL has good immunity for possible frequency drifting due to temperature, process and supply voltage variations. The proposed PLL is designed for −40 to +85 °C, a wide temperature range. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits)

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11 pages, 484 KiB

Open AccessArticle

A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS

by Shengping Lv, Peiyuan Wan, Hongda Zhang, Jiarong Geng, Jiabao Wen, Yiming Yao and Zhijie Chen

Electronics 2021, 10(14), 1668; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10141668 - 13 Jul 2021

Cited by 2 | Viewed by 2458

Abstract

Digital low drop-out regulator (D-LDO) with fast settling time and superior transient response is gaining increasing attention to make up for the deficiency of analog LDO. However, as the traditional digital LDOs regulate the output voltage code at a rate of 1 bit per clock cycle, the transient response speed is limited. In this paper, a multi-bit conversion technique is proposed to improve the transient response speed. The multi-bit conversion technique is achieved by an error detector with adaptive regulation of proportion and integration parameters in the digital controller before pass devices. Besides, a voltage sensor and a time-to-digital converter are employed to convert the output voltage to digital codes. Implemented in a 180-nm CMOS process, the proposed D-LDO features under 36/33 mV of undershoot/overshoot at

V_{OUT}

= 0.95 V as the load current steps up with 40 mA/1 ns on a 0.5 nF load capacitor. The simulated response time is 0.18-ns, the figure-of-merit of speed FOM1 is 0.65 ps and FOM2 achieves 0.068 pF. Full article

(This article belongs to the Special Issue Design of Mixed Analog/Digital Circuits)

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