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State of the Art Networking: From Design to Sensor Applications

A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Communications".

Deadline for manuscript submissions: 1 July 2024 | Viewed by 8701

Special Issue Editors

Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77204-4005, USA
Interests: FPGAs; IoT; fog computing; reconfigurable computing; optical networks; system prototyping
Department of Electrical and Computer Engineering, University of Houston, Houston, TX, USA
Interests: AI for/over wireless networking; cybersecurity; underwater communications and networking underwater IoT
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Guest Editor
Department of Civil and Environmental Engineering, University of Houston, Houston, TX 77204-4003, USA
Interests: smart materials and structures; infrastructural health monitoring

Special Issue Information

Dear Colleagues,

Connected sensors have brought revolutionary changes to manufacturing, personal health management, infrastructure health monitoring, disaster responses, power grid, agriculture, and have affected every walk of life. For example, adding conductive ingredients to construction materials will result in smart infrastructure with self-sensing capability. Unfortunately, the underlying network has not been designed with such a boarder use of connected sensors in mind, which has caused an inefficient use of the network at best, and system wide failure at worst. There is a disconnect between the design of the network and the design of sensor applications. This issue seeks innovations in sensor applications and better network–sensor integration. The areas of interests include, but are not limited to:

  • Novel network–sensor interfaces
  • Application-specific network architecture
  • High-performance sensing platforms
  • Computer vision based infrastructure inspections
  • Sensing technologies for future cities
  • Optimization of resilient networks for smart cities.

Dr. Yuhua Chen
Dr. Miao Pan
Prof. Dr. Yi-Lung Mo
Guest Editors

Manuscript Submission Information

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Published Papers (3 papers)

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Research

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21 pages, 1870 KiB  
Article
Cost-Effective Network Reordering Using FPGA
by Vinh Quoc Hoang and Yuhua Chen
Sensors 2023, 23(2), 819; https://0-doi-org.brum.beds.ac.uk/10.3390/s23020819 - 10 Jan 2023
Viewed by 1613
Abstract
The advancement of complex Internet of Things (IoT) devices in recent years has deepened their dependency on network connectivity, demanding low latency and high throughput. At the same time, expanding operating conditions for these devices have brought challenges that limit the design constraints [...] Read more.
The advancement of complex Internet of Things (IoT) devices in recent years has deepened their dependency on network connectivity, demanding low latency and high throughput. At the same time, expanding operating conditions for these devices have brought challenges that limit the design constraints and accessibility for future hardware or software upgrades. These limitations can result in data loss because of out-of-order packets if the design specification cannot keep up with network demands. In addition, existing network reordering solutions become less applicable due to the drastic changes in the type of network endpoints, as IoT devices typically have less memory and are likely to be power-constrained. One approach to address this problem is reordering packets using reconfigurable hardware to ease computation in other functions. Field Programmable Gate Array (FPGA) devices are ideal candidates for hardware implementations at the network endpoints due to their high performance and flexibility. Moreover, previous research on packet reordering using FPGAs has serious design flaws that can lead to unnecessary packet dropping due to blocking in memory. This research proposes a scalable hardware-focused method for packet reordering that can overcome the flaws from previous work while maintaining minimal resource usage and low time complexity. The design utilizes a pipelined approach to perform sorting in parallel and completes the operation within two clock cycles. FPGA resources are optimized using a two-layer memory management system that consumes minimal on-chip memory and registers. Furthermore, the design is scalable to support multi-flow applications with shared memories in a single FPGA chip. Full article
(This article belongs to the Special Issue State of the Art Networking: From Design to Sensor Applications)
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19 pages, 8610 KiB  
Article
Multi-Physics Mesoscale Substructure Analysis on Stress Wave Measurement within CFST-PZT Coupling Models for Interface Debonding Detection
by Jiang Wang, Bin Xu, Hongbing Chen, Hanbin Ge and Tianmin Zhou
Sensors 2022, 22(3), 1039; https://0-doi-org.brum.beds.ac.uk/10.3390/s22031039 - 28 Jan 2022
Cited by 3 | Viewed by 2052
Abstract
In recent years, the development of interface debonding defect detection methods for concrete-filled steel tubes (CFSTs) using stress wave measurement with piezoelectric-lead-zirconate-titanate (PZT) actuator and sensor has received significant attention. Because the concrete core in CFSTs is a heterogeneous material with randomness at [...] Read more.
In recent years, the development of interface debonding defect detection methods for concrete-filled steel tubes (CFSTs) using stress wave measurement with piezoelectric-lead-zirconate-titanate (PZT) actuator and sensor has received significant attention. Because the concrete core in CFSTs is a heterogeneous material with randomness at the mesoscale, the size, position and distribution of aggregates unavoidably affect the stress wave propagation and the PZT sensor response. In this study, to efficiently investigate the influence of the mesoscale structure of the concrete core of CFSTs on the response of embedded PZT sensors, a multi-physics substructure model of CFST members coupled with a PZT actuator and a PZT sensor, where a single circular aggregate with different size and position and randomly distributed circular aggregates are considered, are established first. Then, multi-physics simulations on the effect of the local mesoscale structure of the concrete core on the response of the embedded PZT sensor excited by both a sinusoidal signal and sweep frequency signal are carried out. Moreover, corresponding multi-physics and mesoscale simulations on the embedded PZT sensor response of substructures with different interface debonding defects are also carried out for comparison. The amplitude and the wavelet packet energy of the embedded PZT sensor response of each mesoscale substructure are employed to distinguish the influence of the concrete core mesoscale structure and interface debonding defect on sensor measurement. The findings from the results with the multi-physics coupling substructure models are compared with those of the full CFST-PZT coupling models and the tested members of the previous studies to verify the rationality of the embedded PZT sensors measurement of the established substructure models. Results from this study show that the effect of interface debonding defect on the amplitude and the wavelet packet energy of the embedded PZT sensor measurement of the CFST members is dominant compared with the mesoscale heterogeneity and randomness of the concrete core. Full article
(This article belongs to the Special Issue State of the Art Networking: From Design to Sensor Applications)
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Review

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18 pages, 269 KiB  
Review
Review of State-of-the-Art FPGA Applications in IoT Networks
by Alexander Magyari and Yuhua Chen
Sensors 2022, 22(19), 7496; https://0-doi-org.brum.beds.ac.uk/10.3390/s22197496 - 02 Oct 2022
Cited by 15 | Viewed by 3967
Abstract
Modern networks used for integrating custom Internet of Things (IoT) systems and devices have restrictions and requirements unique to their individual applications. These application specific demands require custom designed hardware to maximize throughput, security and data integrity whilst minimizing latency, power consumption, and [...] Read more.
Modern networks used for integrating custom Internet of Things (IoT) systems and devices have restrictions and requirements unique to their individual applications. These application specific demands require custom designed hardware to maximize throughput, security and data integrity whilst minimizing latency, power consumption, and form factor. Within this paper, we describe current, state-of-the-art works that utilize FPGAs for IoT network developments. We analyze two categories of works: those that prioritize reducing power consumption, and those that prioritize networking features. Further, we describe how future works can improve upon these designs and therefore improve the efficiency of resource-constrained IoT networks. Full article
(This article belongs to the Special Issue State of the Art Networking: From Design to Sensor Applications)
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