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897 KiB

Open AccessArticle

Assessment of Global Variability in UTBB MOSFETs in Subthreshold Regime

by Sergej Makovejev, Babak Kazemi Esfeh, François Andrieu, Jean-Pierre Raskin, Denis Flandre and Valeriya Kilchytska

J. Low Power Electron. Appl. 2014, 4(3), 201-213; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4030201 - 16 Jul 2014

Cited by 8 | Viewed by 8058

Abstract

The global variability of ultra-thin body and buried oxide (UTBB) MOSFETs in subthreshold and off regimes of operation is analyzed. The variability of the off-state drain current, subthreshold slope, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage and their correlations are considered. [...] Read more.

The global variability of ultra-thin body and buried oxide (UTBB) MOSFETs in subthreshold and off regimes of operation is analyzed. The variability of the off-state drain current, subthreshold slope, drain-induced barrier lowering (DIBL), gate leakage current, threshold voltage and their correlations are considered. Two threshold voltage extraction techniques were used. It is shown that the transconductance over drain current (g_m/I_d) method is preferable for variability studies. It is demonstrated that the subthreshold drain current variability in short channel devices cannot be described by threshold voltage variability. It is suggested to include the effective body factor incorporating short channel effects in order to properly model the subthreshold drain current variability. Full article

(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

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1620 KiB

Open AccessArticle

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

by Masakazu Hioki, Chao Ma, Takashi Kawanami, Yasuhiro Ogasahara, Tadashi Nakagawa, Toshihiro Sekigawa, Toshiyuki Tsutsumi and Hanpei Koike

J. Low Power Electron. Appl. 2014, 4(3), 188-200; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4030188 - 15 Jul 2014

Cited by 8 | Viewed by 9107

Abstract

Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the [...] Read more.

Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB (silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed. Full article

(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

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1348 KiB

Open AccessArticle

Comparative Study of Charge Trapping Type SOI-FinFET Flash Memories with Different Blocking Layer Materials

by Yongxun Liu, Toshihide Nabatame, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'uchi, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Wataru Mizubayashi, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Toyohiro Chikyow and Meishoku Masahara

J. Low Power Electron. Appl. 2014, 4(2), 153-167; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4020153 - 20 Jun 2014

Cited by 6 | Viewed by 15935

Abstract

The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al₂O₃ and SiO₂ have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (V_t [...] Read more.

The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al₂O₃ and SiO₂ have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (V_t) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al₂O₃ blocking layer instead of a SiO₂ blocking layer. It was also confirmed that the variability of V_t before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials. Full article

(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

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469 KiB

Open AccessArticle

MOS Current Mode Logic Near Threshold Circuits

by Alexander Shapiro and Eby G. Friedman

J. Low Power Electron. Appl. 2014, 4(2), 138-152; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4020138 - 11 Jun 2014

Cited by 11 | Viewed by 8944

Abstract

Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML with NTC, the constant power [...] Read more.

Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML) is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET) technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors. Full article

(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

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859 KiB

Open AccessArticle

Analysis of Threshold Voltage Flexibility in Ultrathin-BOX SOI FinFETs

by Kazuhiko Endo, Shinji Migita, Yuki Ishikawa, Takashi Matsukawa, Shin-ichi O'uchi, Junji Tsukada, Wataru Mizubayashi, Yukinori Morita, Hiroyuki Ota, Hitomi Yamauchi and Meishoku Masahara

J. Low Power Electron. Appl. 2014, 4(2), 110-118; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4020110 - 23 May 2014

Cited by 1 | Viewed by 7850

Abstract

A threshold voltage (V_th) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the V_th of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling [...] Read more.

A threshold voltage (V_th) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the V_th of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the V_th controllability in terms of the size dependence such as the gate length (L_G) and the fin width (T_Fin). Full article

(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

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1113 KiB

Open AccessArticle

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

by Pooja Batra, Spyridon Skordas, Douglas LaTulipe, Kevin Winstel, Chandrasekharan Kothandaraman, Ben Himmel, Gary Maier, Bishan He, Deepal Wehella Gamage, John Golz, Wei Lin, Tuan Vo, Deepika Priyadarshini, Alex Hubbard, Kristian Cauffman, Brown Peethala, John Barth, Toshiaki Kirihata, Troy Graves-Abe, Norman Robson and Subramanian Iyer Show full author list Hide full author list

J. Low Power Electron. Appl. 2014, 4(2), 77-89; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4020077 - 05 May 2014

Cited by 16 | Viewed by 11729

Abstract

For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for [...] Read more.

For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation. Full article

(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

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Review

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1151 KiB

Open AccessReview

Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level

by Guerric De Streel and David Bol

J. Low Power Electron. Appl. 2014, 4(3), 168-187; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4030168 - 07 Jul 2014

Cited by 12 | Viewed by 7548

Abstract

Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of back biasing (BB) schemes on these features for 28 nm FDSOI technology at three levels of [...] Read more.

Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of back biasing (BB) schemes on these features for 28 nm FDSOI technology at three levels of abstraction: gate, library and IP. We show that forward BB (FBB) can help cover a wider design space in terms of the optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on the minimum energy point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36× speedup at the MEP. At the IP level, we confirm the MEP configurability with BB with synthesis results of microcontrollers at 0.35 V.We show that the use of a mix of overdrive FBB voltages further improves the energy efficiency. Compared to bulk 65 nm CMOS, we were able 28 nm FDSOI to reduce the energy per cycle by 64% or to increase the frequency of operation by 7×, while maintaining energy per operation below 3 µW/MHz over a wide frequency range. Full article

(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

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1198 KiB

Open AccessReview

An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications

by Arijit Banerjee and Benton H. Calhoun

J. Low Power Electron. Appl. 2014, 4(2), 119-137; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4020119 - 27 May 2014

Cited by 4 | Viewed by 12445

Abstract

Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC) components. Prior work shows [...] Read more.

Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC) components. Prior work shows that operating CMOS circuits at subthreshold supply voltages minimizes energy per operation. However, at subthreshold voltages, SRAM bitcells are sensitive to device variations, and conventional 6T SRAM bitcell is highly vulnerable to readability related errors in subthreshold operation due to lower read static noise margin (RSNM) and half-select issue problems. There are many robust subthreshold bitcells proposed in the literature that have some improvements in RSNM, write static noise margin (WSNM), leakage current, dynamic energy, and other metrics. In this paper, we compare our proposed bitcell with the state of the art subthreshold bitcells across various SRAM design knobs and show their trade-offs in a column mux scenario from the energy and delay metrics and the energy per operation metric standpoint. Our 9T half-select-free subthreshold bitcell has 2.05× lower mean read energy, 1.12× lower mean write energy, and 1.28× lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors. Full article

(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

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441 KiB

Open AccessReview

Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

by Nobuyuki Sugii, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi, Koichiro Ishibashi, Tomoko Mizutani and Toshiro Hiramoto

J. Low Power Electron. Appl. 2014, 4(2), 65-76; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4020065 - 24 Apr 2014

Cited by 11 | Viewed by 8662

Abstract

Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. [...] Read more.

Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive V_th control taking advantage of SOTB’s features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era. Full article

(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)

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